P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z80382, Z8L382
H
IGH
-P
ERFORMANCE
D
ATA
C
OMMUNICATIONS
P
ROCESSORS
FEATURES
s
1
Embedded Z380
ª
Microprocessor
Ð Maintains Object Code Compatibility with Z80
¨
and Z180
ª
Microprocessors
Ð Enhanced Instruction Set for 16-Bit Operation
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
16 MB Linear Addressing
Two Clock Cycle Instruction Execution Minimum
Four On-Chip Register Banks
BC/DE/HL/IX/IY Augmented to 32 Bits
Clock Divide-by-Two and Multiply-by-Two Options
Fully Static CMOS Design with Low-Power
Standby Mode
16-Bit Internal Bus
Dynamic Bus Sizing (8/16-Bit Inter-Operability)
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s
s
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Eight Advanced DMA Channels with 24-Bit Addressing
Plug-and-Play ISA Interface
PCMCIA Interface
Two Enhanced ASCIs (UARTs) with 16-Bit Baud Rate
Generators (BRG)
Clocked Serial I/O Channel (CSIO) for Use with Serial
Memory
Two 16-Bit Timers with Flexible Prescalers
Three Memory Chip Selects with Wait-State Generators
Watch-Dog Timer (WDT)
Up to 32 General-Purpose I/O Pins
DC to 20 MHz Operating Frequency @ 5.0V
DC to 10 MHz Operating Frequency @ 3.3V
144-Pin QFP and VQFP Style Packages
s
s
s
s
s
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s
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16550 Mimic with I/O Mailbox, DMA Mailbox, and 16 mA
Bus Drive
Three HDLC Synchronous Serial Channels
Ð Serial Data Rate of up to 10 Mbps
GCI/SCIT Bus Interface
s
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GENERAL DESCRIPTION
The Z80382 (Z382) is designed to address high-end data
communication applications such as digital modems (IS-
DN, GSM, Mobitex & Modacom), xDSL and analog mo-
dems (V.34 and beyond). The Z382 provides a perfor-
mance upgrade to existing Z80- and Z18x-based designs
by utilizing the increased bandwidth of the 380C proces-
sor. The Z8L382 is a low voltage version of the device.
Note:
In this document the notation Ò380CÓ denotes the
Z380-compatible CPU core which is embedded in the
Z382.
The 380C microprocessor is a high-performance proces-
sor with fast and efficient throughput and increased mem-
ory addressing capabilities. The 380C offers a continuing
growth path for present Z80- or Z18x-based designs, while
maintaining Z80 and Z180 object code compatibility. Its en-
hancements include added instructions, expanded16 MB
address space and flexible bus interface timing.
In the 380C, the basic addressing modes of the Z80 micro-
processor have been augmented to include Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing. Inter-
nally, all of the addressing modes allow up to 32-bit linear
addressing; however, because the Z382 has only 24 ad-
dress pins, it can only address 16 MB of memory.
DS97Z382000
PRELIMINARY
1
Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
GENERAL DESCRIPTION
(Continued)
Other additions to the instruction set include a full comple-
ment of 16-bit arithmetic and logical operations, 16-bit I/O
operations, multiply and divide, and a complete set of reg-
ister-to-register loads and exchanges.
The 380C register file includes alternate versions of the IX
and IY registers. There are four banks of registers in the
380C, along with instructions for switching among them.
All of the 16-bit register pairs and index registers in the ba-
sic Z80 microprocessor register file are expanded to 32
bits.
The Z382 includes dynamic bus sizing to allow any mix of
16- and 8-bit memory, and I/O devices in a system. One
application for this capability would be to copy code from a
low-cost, slow 8-bit ROM to 16-bit RAM, from which it can
be executed at much higher speeds. Memory bus sizes
can be configured internally by software to eliminate the
need for external logic to drive MSIZE.
Some features that have traditionally been handled by ex-
ternal peripherals have been incorporated in the Z382.
These on-chip peripherals reduce system chip count and
interconnections on the external bus. These peripherals, il-
lustrated in the Z382 Block Diagram in Figure 1, are sum-
marized below.
HDLC Synchronous Channels.
Three HDLC channels
operate at serial data rates of up to 10 Mbps and feature
8-byte receive and transmit FIFOs. These can be used for
modems, general data communications, and ISDN. The
ISDN can be handled separately or through the GCI/SCIT
bus interface. HDLC Channels always transfer data
through the DMA channels. A transparent mode is select-
able. Two of the HDLC cells can be pin multiplexed with
the ASCIs (UARTs) to provide dynamically switchable
(async-sync) DTE interfaces.
DMA Channels
. The eight DMA channels provide 24-bit
memory addressing and can transfer memory block sizes
of up to 64 KB (16-bits). These DMA channels can be dy-
namically assigned to serve the HDLC ports, Mimic COM
port, Host DMA Mailbox, or ASCIs in any mixture. Linked
list operation allows all HDLC transmitters and receivers to
operate at or above E1 rates simultaneously without load-
ing the bus bandwidth.
16550 Mimic
. Provides connection to a PC ISA bus and
emulation of the 16550 UART register set. Improvements
include 16 mA output drivers and internal COM port ad-
dress decoding to reduce external PC interface compo-
nents.
ASCI
. Two flexible asynchronous serial channels with
baud rate generators, modem control and status.
CSIO
. A clocked serial I/O channel which can be used for
serial memory interface.
Timers
. Two 16-bit counter/timers with flexible prescalers
for wide-range timing applications.
GCI/SCIT Bus Interface
. A common interface to ISDN in-
terface devices. Internal signals from this module can be
connected to the HDLC channels to provide B-channels
and D-channel for ISDN.
Plug-and-Play ISA Interface
. Provides auto-configura-
tion in ISA (AT bus) applications.
PCMCIA Interface
. Provides connectivity to a PCMCIA
bus.
32-Bit General-Purpose I/O
. For non-PC add-in applica-
tions, four 8-bit ports are provided for general- purpose I/O.
In ISA or PCMCIA applications, the pins from two of the
ports are reallocated to host bus signals and are not avail-
able. Pins from the other two ports are selectively multi-
plexed with on-chip peripheral functions (ASCIs, CSI/O,
PRT). These pins are individually programmable for in-
put/output mode.
I/O Chip Selects.
Two I/O chip selects are provided to
support I/O access of external peripherals. Each has a pro-
grammable base address and provides I/O decode sizes
ranging from 8 to 512 bytes.
ROM/RAM Chip Selects with Wait-State Generators
.
Chip select outputs are provided to decode memory ad-
dresses and provide memory chip enables. Each chip se-
lect has its own Wait State Generator to allow use of mem-
ories with different speeds.
Watch-Dog Timer
. A Watch-Dog Timer (WDT) with a wide
range of time-constants prevents code runaway and pos-
sible resulting system damage. The /RESET input can be
forced as an output upon the terminal count of the WDT.
This allows external peripherals to be reset along with the
Z382.
2
PRELIMINARY
DS97Z382000
Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
IN
T
OPR
T
STG
Description
Supply Voltage
Input Voltage
Operating Temp
Storage Temp
Value
-0.3 to +7.0
-0.3 to V
DD
+0.3
0 to +70
-55 to +150
Unit
V
V
°
C
°
C
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for extended periods
may affect device reliability.
1
STANDARD TEST CONDITIONS
The DC Characteristics which follow apply for the following
standard test conditions, unless otherwise noted. All volt-
ages are referenced to GND (0V). Positive current flows
into the referenced pin (Figure 3, Test Load Diagram).
s
I
OL
= 2 mA
Operating temperature range:
Ð Standard: 0
°
C to 70
°
C
1.4V
Voltage Supply Range:
Ð +4.5V
£
V
DD
£
+5.5V (Z80382 versions)
Ð +3.0V
£
V
DD
£
+3.6V (Z8L382 versions)
All AC parameters assume a load capacitance of 50 pF.
Add 10 ns delay for each 50 pF increase in load up to a
maximum of 150 pF for the data bus and 100 pF for ad-
dress and control lines. AC timing measurements are ref-
erenced to 1.5 volts (except for clock, which is referenced
to the 10% and 90% points). Maximum capacitive load for
PHI is 125 pF.
s
100 pF
I
OH
= 250
mA
Figure 3. Test Load Diagram
DS97Z382000
PRELIMINARY
5
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