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DESCRIPTION
The WM8960 is a low power, high quality stereo CODEC
designed for portable digital audio applications.
Stereo class D speaker drivers provide 1W per channel into 8
loads with a 5V supply. Low leakage, excellent PSRR and
pop/click suppression mechanisms also allow direct battery
connection to the speaker supply. Flexible speaker boost
settings allow speaker output power to be maximised while
minimising other analogue supply currents.
A highly flexible input configuration for up to three stereo
sources is integrated, with a complete microphone interface.
External component requirements are drastically reduced as no
separate microphone, speaker or headphone amplifiers are
required. Advanced on-chip digital signal processing performs
automatic level control for the microphone or line input.
Stereo 24-bit sigma-delta ADCs and DACs are used with low
power over-sampling digital interpolation and decimation filters
and a flexible digital audio interface.
The master clock can be input directly or generated internally by
an onboard PLL, supporting most commonly-used clocking
schemes.
The WM8960 operates at analogue supply voltages down to
2.7V, although the digital supplies can operate at voltages down
to 1.71V to save power. The speaker supply can operate at up
to 5.5V, providing 1W per channel into 8 loads. Unused
functions can be disabled using software control to save power.
The WM8960 is supplied in a very small and thin 5x5mm QFN
package, ideal for use in hand-held and portable systems.
DGND
Jack Detect
WM8960
Stereo CODEC with 1W Stereo Class D Speaker Drivers and
Headphone Drivers for Portable Audio Applications
FEATURES
DAC SNR 98dB (‘A’ weighted), THD -84dB at 48kHz, 3.3V
ADC SNR 94dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V
Pop and click suppression
3D Enhancement
Stereo Class D Speaker Driver
-
<0.1% THD with 1W per channel into 8 BTL speakers
-
70dB PSRR @217Hz
-
87% efficiency (1W output)
-
Flexible internal switching clock
On-chip Headphone Driver
-
40mW output power into 16 at 3.3V
-
Capless mode support
-
THD -75dB at 20mW, SNR 90dB with 16 load
Microphone Interface
-
Pseudo differential for high noise immunity
-
Integrated low noise MICBIAS
-
Programmable ALC / Limiter and Noise Gate
Low Power Consumption
Low Supply Voltages
-
Analogue 2.7V to 3.6V (Speaker supply up to 5.5V)
-
Digital core and I/O: 1.71V to 3.6V
On-chip PLL provides flexible clocking scheme
Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48
5x5x0.9mm QFN package
APPLICATIONS
Games consoles
Portable media / DVD players
Mobile multimedia
DCVDD
DBVDD
0 to -21dB,
3dB steps
0 to -21dB,
3dB steps
-73 to 6dB
1dB steps,
mute
+BOOST
LINPUT3/
JD2
LINPUT2
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WM8960
CLASS D
SPKVDD1
SPKVDD2
SPK_LP
SPK_LN
-12 -> 6dB,
3dB steps,
mute
-17.25 to +30dB,
0.75dB steps
-12 -> 6dB,
3dB steps,
mute
LEFT
MIXER
+
vmid
-
0, 13, 20,
29dB,
mute
+
INPUT
PGAs
ADC
LINPUT1
ADC
DIGITAL
FILTERS
ALC
DAC
DIGITAL
FILTERS
DE-
EMPHASIS
3D ENHANCE
VOLUME
DAC
-73 to 6dB
1dB steps,
mute
HP_L
MONO
MIXER
0dB / -6dB
OUT3
RINPUT1
vmid
-
+
-17.25 to +30dB,
0.75dB steps
0, 13, 20,
29dB,
mute
VOLUME
+
-12 -> 6dB,
3dB steps,
mute
ADC
DAC
RIGHT
MIXER
0 to -21dB,
3dB steps
0 to -21dB,
3dB steps
-73 to 6dB
1dB steps,
mute
+BOOST
-73 to 6dB
1dB steps,
mute
HP_R
-12 -> 6dB,
3dB steps,
mute
RINPUT2
RINPUT3/
JD3
Jack Detect
ADCREF,
DACREF
50K
50K
CLASS D
SPK_RN
SPK_RP
GPIO1
MICBIAS
DIGITAL AUDIO
INTERFACE
A-law and u-law support
PLL
CONTROL
INTERFACE
SPKGND1
SPKGND2
AGND
AVDD
VMID
BCLK
ADCLRC/GPIO1
ADCDAT
DACLRC
DACDAT
MCLK
WOLFSON MICROELECTRONICS plc
Production Data, August 2013, Rev 4.2
Copyright
2013
Wolfson Microelectronics plc
SCLK
SDIN
WM8960
TABLE OF CONTENTS
Production Data
DESCRIPTION ....................................................................................................... 1
FEATURES ............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION .......................................................................................... 3
ORDERING INFORMATION .................................................................................. 3
PIN DESCRIPTION ................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS ........................................................................ 5
RECOMMENDED OPERATING CONDITIONS ..................................................... 5
ELECTRICAL CHARACTERISTICS ..................................................................... 6
OUTPUT PGA GAIN ............................................................................................ 10
TYPICAL POWER CONSUMPTION.................................................................... 11
SIGNAL TIMING REQUIREMENTS .................................................................... 13
SYSTEM CLOCK TIMING .............................................................................................. 13
AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 13
AUDIO INTERFACE TIMING – SLAVE MODE .............................................................. 14
CONTROL INTERFACE TIMING – 2-WIRE MODE ....................................................... 15
INTERNAL POWER ON RESET CIRCUIT .......................................................... 16
DEVICE DESCRIPTION ...................................................................................... 18
INTRODUCTION ............................................................................................................ 18
INPUT SIGNAL PATH .................................................................................................... 19
ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................................ 26
AUTOMATIC LEVEL CONTROL (ALC) ......................................................................... 28
OUTPUT SIGNAL PATH ................................................................................................ 31
ANALOGUE OUTPUTS ................................................................................................. 37
ENABLING THE OUTPUTS ........................................................................................... 41
HEADPHONE OUTPUT ................................................................................................. 41
CLASS D SPEAKER OUTPUTS .................................................................................... 42
VOLUME UPDATES ...................................................................................................... 43
HEADPHONE JACK DETECT ....................................................................................... 45
THERMAL SHUTDOWN ................................................................................................ 46
GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 47
DIGITAL AUDIO INTERFACE ........................................................................................ 48
AUDIO INTERFACE CONTROL .................................................................................... 52
CLOCKING AND SAMPLE RATES................................................................................ 56
CONTROL INTERFACE................................................................................................. 63
POWER MANAGEMENT ............................................................................................... 63
REGISTER MAP .................................................................................................. 67
REGISTER BITS BY ADDRESS .................................................................................... 68
DIGITAL FILTER CHARACTERISTICS .............................................................. 82
ADC FILTER RESPONSES ........................................................................................... 83
DAC FILTER RESPONSES ........................................................................................... 83
DE-EMPHASIS FILTER RESPONSES .......................................................................... 85
APPLICATIONS INFORMATION ........................................................................ 86
RECOMMENDED EXTERNAL COMPONENTS ............................................................ 86
IMPORTANT NOTICE ......................................................................................... 90
ADDRESS: ..................................................................................................................... 90
REVISION HISTORY ........................................................................................... 91
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Production Data
WM8960
PIN CONFIGURATION
32
31
30
29
28
27
26
25
24
SPKGND1
23
22
21
MICBIAS
LINPUT3/JD2
LINPUT2
LINPUT1
RINPUT1
RINPUT2
RINPUT3/JD3
DCVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SPK_LN
SPK_RP
SPKVDD2
SPKGND2
SPK_RN
SDIN
SCLK
TOP VIEW
20
19
18
17
ORDERING INFORMATION
ORDER CODE
WM8960CGEFL/V
WM8960CGEFL/RV
WM8960CGEFL/2RV
Note:
Reel quantity = 3500 (WM8960CGEFL/V and WM8960CGEFL/RV)
Reel quantity = 2200 (WM8960CGEFL/2RV)
TEMPERATURE RANGE
-40C to +85C
-40C to +85C
-40C to +85C
PACKAGE
32-lead QFN (5x5x0.9mm)
(Pb-free)
32-lead QFN (5x5x0.9mm)
(Pb-free, Tape and reel)
32-lead QFN (5x5x0.9mm)
(Pb-free, Tape and reel)
MSL3
MSL3
260°C
260°C
MOISTURE
SENSITIVITY LEVEL
MSL3
PEAK SOLDERING
TEMPERATURE
260°C
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WM8960
PIN DESCRIPTION
PIN NO
1
2
MICBIAS
LINPUT3 / JD2
NAME
TYPE
Analogue Output
Analogue Input
Microphone bias
Left channel line input /
Left channel positive differential MIC input /
Jack detect input pin
3
4
5
6
7
LINPUT2
LINPUT1
RINPUT1
RINPUT2
RINPUT3 / JD3
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Left channel line input /
Left channel positive differential MIC input
Left channel single-ended MIC input /
Left channel negative differential MIC input
Right channel single-ended MIC input /
Right channel negative differential MIC input
Right channel line input /
Right channel positive differential MIC input
Right channel line input /
Right channel positive differential MIC input /
Jack detect input pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Note:
1.
DCVDD
DGND
DBVDD
MCLK
BCLK
DACLRC
DACDAT
ADCLRC / GPIO1
ADCDAT
SCLK
SDIN
SPK_RN
SPKGND2
SPKVDD2
SPK_RP
SPK_LN
SPKGND1
SPK_LP
SPKVDD1
VMID
AGND
HP_R
OUT3
HP_L
AVDD
GND_PADDLE
Supply
Supply
Supply
Digital Input
Digital Input / Output
Digital Input / Output
Digital Input
Digital Input / Output
Digital Output
Digital Input
Digital Input/Output
Analogue Output
Supply
Supply
Analogue Output
Analogue Output
Supply
Analogue Output
Supply
Analogue Output
Supply
Analogue Output
Analogue Output
Analogue Output
Supply
Digital core supply
DESCRIPTION
Production Data
Digital ground (Return path for both DCVDD and DBVDD)
Digital buffer (I/O) supply
Master clock
Audio interface bit clock
Audio interface DAC left / right clock
DAC digital audio data
Audio interface ADC left / right clock / GPIO1 pin
ADC digital audio data
Control interface clock input
Control interface data input / 2-wire acknowledge output
Right speaker negative output
Ground for speaker drivers 2
Supply for speaker drivers 2
Right speaker positive output
Left speaker negative output
Ground for speaker drivers 1
Left speaker positive output
Supply for speaker drivers 1
Midrail voltage decoupling capacitor
Analogue ground (Return path for AVDD)
Right output (Line or headphone)
Mono, left, right or buffered midrail output for capless mode
Left output (Line or headphone)
Analogue supply
Die Paddle (Note 1)
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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Production Data
WM8960
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages (excluding SPKVDD1 and SPKVDD2)
SPKVDD1, SPKVDD2
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T
A
Storage temperature after soldering
Notes:
1.
2.
3.
4.
5.
Analogue, digital and speaker grounds must always be within 0.3V of each other.
All digital and analogue supplies are completely independent from each other (i.e. not internally connected).
DCVDD must be less than or equal to AVDD and DBVDD.
AVDD must be less than or equal to SPKVDD1 and SPKVDD2.
SPKVDD1 and SPKVDD2 must be high enough to support the peak output voltage when using DCGAIN and ACGAIN
functions, to avoid output waveform clipping. Peak output voltage is AVDD*(DCGAIN+ACGAIN)/2.
MIN
-0.3V
-0.3V
DGND -0.3V
AGND -0.3V
-40C
-65C
MAX
+4.5V
+7V
DBVDD +0.3V
AVDD +0.3V
+85C
+150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Speaker supply range
Ground
SYMBOL
DCVDD
DBVDD
AVDD
SPKVDD1, SPKVDD2
DGND, AGND, SPKGND1,
SPKGND2
MIN
1.71
1.71
2.7
2.7
0
TYP
MAX
3.6
3.6
3.6
5.5
UNIT
V
V
V
V
V
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