CMOS Dual Channel
UART (DUART)
June 2006
XR88C681
FEATURES
D
Two Full Duplex, Independent Channels
D
Asynchronous Receiver and Transmitter
D
Quadruple-Buffered Receivers and Dual Buffered
Transmitters
D
Programmable Stop Bits in 1/16 Bit Increments
D
Internal Bit Rate Generators with More than 23 Bit
Rates
D
Independent Bit Rate Selection for Each Transmitter
and Receiver
D
External Clock Capability
D
Maximum Bit Rate: 1X Clock - 1Mb/s, 16X Clock -
125kb/s
D
Normal, AUTOECHO, Local LOOPBACK and
Remote LOOPBACK Modes
D
Multi-function 16 Bit Counter/Timer
D
Interrupt Output with Eight Maskable Interrupt
Conditions
D
Interrupt Vector Output on Acknowledge (40 Pin DIP
and 44 Pin PLCC Packages Only)
GENERAL DESCRIPTION
The EXAR Dual Universal Asynchronous Receiver and
Transmitter (DUART) is a data communications device that
provides two fully independent full duplex asynchronous
communication channels in a single package. The DUART
is designed for use in microprocessor based systems and
may be used in a polled or interrupt driven environment.
The XR88C681 device offers a single IC solution for the
8080/85, 8086/88, Z80, Z8000, 68xx and 65xx
microprocessor families.
ORDERING INFORMATION
Part No.
XR88C681CJ
XR88C681CN/40
XR88C681CP/28
XR88C681CP/40
XR88C681J
XR88C681N/40
XR88C681P/28
XR88C681P/40
Rev. 2.11
E2006
D
Programmable Interrupt Daisy Chain
D
8 General Purpose Outputs (40 Pin DIP and 44 Pin
PLCC Packages Only)
D
7 General Purpose Inputs with Change of States
Detectors on Inputs (40 Pin DIP and 44 Pin PLCC
Packages Only)
D
Multi-Drop Mode Compatible with 8051 Nine Bit
Mode
D
On-Chip Oscillator for Crystal
D
Standby Mode to Reduce Operating Power
D
Compatible with the Motorola MC2681 and
Signetics SCC2692 devices
D
Advanced CMOS Low Power Technology
APPLICATIONS
D
Multimedia Systems
D
Serial to Parallel/Parallel to Serial Converter
D
DTE for Modem Communication Systems
The DUART is fabricated using advanced two layer metal,
with a high performance density EPI/CMOS 1.8 process
to provide high performance and low power consumption,
and is packaged in a 40 pin PDIP, a 28 pin PDIP, and a 44
pin PLCC.
Pin Package
44 PLCC
40 CDIP
28 PDIP
40 PDIP
44 PLCC
40 CDIP
28 PDIP
40 PDIP
Operating
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
XR88C681
TXDA
RXDA
TXDB
RXDB
IP0 - IP6
OP0 - OP7
TSR
RSR
TSR
RSR
IPR
Change of
State Detectors
IPCR
OPR
Output Port
Function Select
Logic
OPCR
THR
RHR
THR
RHR
Mode Registers
Status Register
Channel A
Mode Registers
Status Register
Channel B
ACR
Input Port
Output Port
Internal Data Bus
Operation Control
Interrupt Control
IVR
CSRA
Timing
CSRB
Bit Rate
Generator
Counter/Timer
Oscillator
Data
Bus
Buffer
CRA
CRB
MISR
IMR
ISR
Command Decoder
Address Decoder
D0 - D7
A0 - A3
-RD -WR
-CS RESET
IEI IEO -IACK -INTR
X1/CLK
X2
Figure 1. Block Diagram of the XR88C681
Rev. 2.11
2
XR88C681
PIN CONFIGURATION
41 -IP6/IACK
42 IP5/IEO
44 Vcc
43 IP4/IEI
A3
IP0
-WR
-RD
RXDB
NC
TXDB
OP1
OP3
OP5
OP7
7
8
9
10
11
12
13
14
15
16
17
D3 19
D5 20
D1 18
39 CS
38 -RESET
37 X2
36 X1/CLK
35 RXDA
XR-68C681CJ
PLCC
A0
IP3
A1
IP1
A2
A3
IP0
-WR
-RD
RXDB
TXDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
IP4/IEI
IP5/IEO
-IP6/IACK
IP2
-CS
RESET
X2
X1/CLK
RXDA
TXDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
-INTR
1 NC
5 IP1
3 IP3
40 IP2
34
33
32
31
6 A2
4 A1
2
A0
NC
TXDA
OP0
OP2
30 OP4
29 OP6
D7 21
D4 26
D2 27
NC 23
GND 22
-INTR 24
D0 28
D6 25
44 Lead PLCC
40 Lead PDIP, CDIP (0.600”)
A0
A1
A2
A3
-WR
-RD
RXDB
TXDB
OP1
D1
D3
D5
D7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
IP2
-CS
RESET
X2
X1/CLK
RXDA
TXDA
OP0
D0
D2
D4
D6
-INTR
28 Lead PDIP (0.600”)
Rev. 2.11
3
XR88C681
PIN DESCRIPTION
44 PLCC
1
2
1
1
40 PDIP,
CDIP
28 PDIP
Symbol
NC
A0
I
Type
Description
No Connection.
LSB of Address Input.
This input, along with Address Inputs,
A1 - A3 are used to select certain registers within the DUART
device, during READ and WRITE operations with the CPU.
Input Port 3.
General Purpose Input - When the DUART is
operating in the I-mode, this input can also be used as the
external clock input for the Channel A Transmitter (TXCA).
When the DUART is operating in the Z-Mode, this input can
be used as the external clock input for the Channel A Receiv-
er (RXCA).
4
5
3
4
2
A1
IP1
(-CTSB)
3
4
A2
A3
I
I
Address Input.
Input Port 1.
General Purpose Input - This input can also be
used as the Active Low, “Channel B Clear to Send” input.
(
-
CTSB)
Address Input.
MSB of Address Input.
This input, along with Address In-
puts, A0 - A2 are used to select certain registers within the
DUART device, during READ and WRITE operations with the
CPU.
Input 0.
General Purpose Input - This input can also be used
as the active-low, “Channel A Clear-to-Send” input. (-CTSA)
Write Strobe (Active-Low).
A “low” on this input while -CS is
also “low” writes the contents of the Data Bus into the ad-
dressed register, within the DUART. The transfer occurs on
the rising edge of -WR.
Read Strobe (Active Low).
A “low” on this input while
-
CS is
also “low” places the contents of the addressed DUART regis-
ter, on the data bus.
Receive Serial Data Input (Channel B).
The least significant
bit of the character is received first. If external receiver clock,
RXCB, is specified, the data is sampled on the rising edge of
this clock.
No Connect.
O
Transmitter Serial Data Output (Channel B).
The least sig-
nificant bit of the character is transmitted first. This output is
held in the high (marking state) when the transmitter is idle,
disabled, or when the channel is operating in the local LOOP-
BACK mode. If an external transmitter clock is specified,
TXCB, the transmitted data is shifted out of the TSR (Trans-
mitter Shift Register) on the falling the edge of this clock.
3
2
IP3
(TXCA - I)
(RXCA - Z)
I
6
7
5
6
I
I
8
9
7
8
5
IP0
(-CTSA)
-WR
I
I
10
9
6
-RD
I
11
10
7
RXDB
I
12
13
11
8
NC
TXDB
Rev. 2.11
4
XR88C681
44 PLCC
14
40 PDIP,
CDIP
12
28 PDIP
9
Symbol
OP1
(-RTSB)
OP3
(TXCB_1X)
(RXCB_1X)
(-C/T_RDY)
OP5
(-RXRDY/
-FFULL_B)
OP7
(TXRDY_B)
Type
O
Description
Output 1 (General Purpose Output).
This output can also
be programmed to function as the active-low, “Channel B
Request-to-Send” Output (-RTSB).
Output 3 (General Purpose Output).
This output port can
also be programmed to function as: the “Channel B Trans-
mitter 1X clock” output (TXCB_1X), the “Channel B Receiv-
er 1X clock” output (RXCB_1X), or the open drain, active-
low “Counter/Timer Ready” output (-C/T_RDY).
Output 5 (General Purpose Output Pin).
This output port
pin can also be programmed to function as the open-drain,
active-low, Channel B “Receive Ready” or “Receiver FIFO
Full” indicator output (-RXRDY_B/-FFULL_B).
Output 7. (General Purpose Output Pin).
This output port
pin can also be programmed to function as the open-drain,
active-low, “Transmitter Ready” indicator output for Channel
B (
-
TXRDY_B).
Bi-Directional Data Bus.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
MSB of the Eight Bit Bi-Directional Data Bus.
All transfers
between the CPU and the DUART take place over this bus
(consisting of pins D0 - D7). The bus is tri-stated when the
-
CS input is “high”, except during an IACK cycle (in the Z-
Mode).
Signal Ground.
No Connect.
O
Interrupt Request Output (Active Low, Open Drain).
-
INTR is asserted upon the occurrence of one or more of the
chip’s maskable interrupting conditions. This signal will re-
main asserted throughout the Interrupt Service Routine and
will be negated once the condition(s) causing the Interrupt
Request has been eliminated.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
LSB of the Eight Bit Bi-Directional Data Bus.
All transfers
between the CPU and the DUART take place over this bus.
The bus is tri-stated when the
-
CS input is “high”, except
during an IACK cycle (in the Z-Mode).
Output 6 (General Purpose Output).
This output pin can
also be programmed to function as the open drain, active-
low, “Transmitter Ready” indicator output for Channel A
(
-
TXRDY_A).
15
13
O
16
14
O
17
15
O
18
19
20
21
16
17
18
19
10
11
12
13
D1
D3
D5
D7
I/O
I/O
I/O
I/O
22
23
24
20
21
14
15
GND
NC
-
INTR
PWR
25
26
27
28
22
23
24
25
16
17
18
19
D6
D4
D2
D0
I/O
I/O
I/O
I/O
29
26
OP6
(-TXRDY_A)
O
Rev. 2.11
5
京公网安备 11010802033920号
EEWORLD
