Data Sheet
FEATURES
RF output frequency range: 53.125 MHz to 13,600 MHz
Noise floor integer channel: −227 dBc/Hz
Noise floor fractional channel: −225 dBc/Hz
Integrated rms jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output
Fractional-N synthesizer and integer N synthesizer
Pin compatible to the
ADF5355
High resolution, 52-bit modulus
Phase frequency detector (PFD) operation to 125 MHz
Reference input frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable output power level
RF output mute function
Supported by the
ADIsimPLL
design tool
Microwave Wideband Synthesizer
with Integrated VCO
ADF5356
GENERAL DESCRIPTION
The ADF5356 allows implementation of fractional-N or integer N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. The
wideband microwave VCO design permits frequency operation
from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A
series of frequency dividers at another frequency output permits
operation from 53.125 MHz to 6800 MHz.
The ADF5356 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 53.125 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin- and software-controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF5356 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF5356 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS)
Point to point and point to multipoint microwave links
Satellites and very small aperture terminals (VSATs)
Test equipment and instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
CE
AV
DD
AV
DD
DV
DD
V
P
R
SET
V
VCO
V
RF
REF
IN
A
REF
IN
B
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
MULTIPLEXER
LOCK
DETECT
CHARGE
PUMP
PHASE
COMPARATOR
MUXOUT
C
REG
1
C
REG
2
CP
OUT
V
TUNE
V
REF
×2
OUTPUT
STAGE
V
BIAS
V
REGVCO
RF
OUT
B
PDB
RF
CLK
DATA
LE
DATA REGISTER
FUNCTION
LATCH
INTEGER
REG
FRACTION
REG
MODULUS
REG
VCO
CORE
THIRD-ORDER
FRACTIONAL INTERPOLATOR
÷ 1/2/4/8/
16/32/64
N COUNTER
OUTPUT
STAGE
RF
OUT
A+
RF
OUT
A–
MULTIPLEXER
A
GND
CP
GND
A
GNDRF
SD
GND
A
GNDVCO
ADF5356
15360-001
Figure 1.
Rev. 0
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ADF5356
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Transistor Count ........................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 15
Reference Input Section ............................................................. 15
RF N Divider ............................................................................... 15
Phase Frequency Detector (PFD) and Charge Pump ............ 16
MUXOUT and Lock Detect ...................................................... 16
Input Shift Registers ................................................................... 16
Program Modes .......................................................................... 17
VCO.............................................................................................. 17
Output Stage ................................................................................ 17
Register Maps .................................................................................. 19
Register 0 ..................................................................................... 21
Register 1 ..................................................................................... 22
Register 2 ..................................................................................... 22
Data Sheet
Register 3 ..................................................................................... 23
Register 4 ..................................................................................... 24
Register 5 ..................................................................................... 25
Register 6 ..................................................................................... 26
Register 7 ..................................................................................... 28
Register 8 ..................................................................................... 29
Register 9 ..................................................................................... 29
Register 10 ................................................................................... 30
Register 11 ................................................................................... 31
Register 12 ................................................................................... 31
Register 13 ................................................................................... 32
Register Initialization Sequence ............................................... 32
Frequency Update Sequence ..................................................... 33
RF Synthesizer—A Worked Example ...................................... 33
Reference Doubler and Reference Divider ............................. 34
Spurious Optimization and Fast Lock ..................................... 34
Optimizing Jitter......................................................................... 34
Spur Mechanisms ....................................................................... 34
PLL Lock Time ........................................................................... 34
Applications Information .............................................................. 36
Power Supplies ............................................................................ 36
PCB Design Guidelines for a Chip Scale Package ................. 36
Output Matching ........................................................................ 37
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
8/2017—Revision
0: Initial Version
Rev. 0 | Page 2 of 38
Data Sheet
SPECIFICATIONS
ADF5356
AV
DD
= DV
DD
= V
RF
= 3.3 V ±5%, 4.75 V ≤ V
P
= V
VCO
≤ 5.25 V, A
GND
= CP
GND
= A
GNDVCO
= SD
GND
= A
GNDRF
= 0 V, R
SET
= 5.1 kΩ, dBm referred
to 50 Ω, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
REF
IN
A/REF
IN
B CHARACTERISTICS
Input Frequency Range
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Differential Mode
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
For f < 10 MHz, ensure slew rate > 21 V/μs
10
10
0.4
0.4
250
600
AV
DD
1.8
MHz
MHz
V p-p
V p-p
REF
IN
A biased at AV
DD
/2; ac coupling ensures
AV
DD
/2 bias
Low voltage differential signaling (LVDS) and
Low voltage positive emitter-coupled logic
(LVPECL) compatible, REF
IN
A/REF
IN
B biased at
2.1 V; ac coupling ensures 2.1 V bias
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
PFD
CHARGE PUMP (CP)
CP Current, Sink/Source
High Value
Low Value
R
SET
Range
Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
Input Voltage
High
Low
Input Current, High/Low
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply
Voltage
CP and VCO Supply Voltage
Total Digital and Analog Current,
DI
DD
+ AI
DD3
Output Dividers
CP Supply Power Current
Supply Current
6.9
1.4
±100
±250
125
I
CP
4.8
0.3
5.1
3
3
1.5
pF
pF
μA
μA
MHz
Single-ended reference programmed
Differential reference programmed
R
SET
= 5.1 kΩ, this resistor is internal in the
ADF5356
mA
mA
kΩ
%
%
%
Fixed
0.5 V ≤ V
CP1
≤ V
P
− 0.5 V
0.5 V ≤ V
CP1
≤ V
P
− 0.5 V
V
CP1
= 2.5 V
V
INH
V
INL
I
INH
/I
INL
C
IN
V
OH
I
OH
V
OL
AV
DD
DV
DD
,
V
RF
V
P
, V
VCO
1.5
DV
DD
0.6
±1
3.0
V
V
μA
pF
V
V
μA
V
V
Voltages must equal AV
DD
3.3 V output selected
1.8 V output selected
I
OL2
= 500 μA
See Table 7
DV
DD
− 0.4
1.5
1.8
500
0.4
3.15
3.3
AV
DD
5.0
82
6 to 36
8
70
3.45
4.75
5.25
92
V
mA
mA
V
P
must equal V
VCO
I
P
I
VCO
9
90
Each output divide by 2 consumes 6 mA
For maximum I
CP
= 4.8 mA
mA
Rev. 0 | Page 3 of 38
ADF5356
Parameter
RF
OUT
A+/RF
OUT
A− and RF
OUT
B Supply
Current
Symbol
I
RFOUTx±
Min
Typ
Max
Unit
Data Sheet
Test Conditions/Comments
RF Output A and RF Output B enabled;
RF Output A is programmable; enabling RF
Output B draws negligible extra current
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
Hardware power-down selected
Software power-down selected
Fundamental VCO range
2× VCO output (RF
OUT
B), prescaler = 8/9
2× VCO output (RF
OUT
B), prescaler = 4/5
Prescaler = 8/9
Prescaler = 4/5
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF
OUT
B Output Frequency
RF
OUT
A+/RF
OUT
A− Output
Frequency
VCO Sensitivity
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
K
V
12
24
35
46
5
20
3400
6800
6800
53.125
53.125
25
12
0.5
30
15
29
42
56
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz/V
MHz/V
MHz
MHz
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dBm
dB
dB
dB
dB
dBm
dBm
dBm
dBm
6800
13600
12000
6800
6000
Voltage standing wave ratio (VSWR) = 2:1
RF
OUT
A/RF
OUT
A−
VSWR = 2:1 RF
OUT
B
Fundamental VCO output (RF
OUT
A+)
Divided VCO output (RF
OUT
A+)
Fundamental VCO output (RF
OUT
A+)
Divided VCO output (RF
OUT
A+)
RF
OUT
B = 10 GHz
RF
OUT
A+ = 1 GHz; 7.4 nH inductor to V
RF
RF
OUT
A+ = 6.8 GHz; 7.4 nH inductor to V
RF
RF
OUT
B = 6.8 GHz
RF
OUT
B = 13.6 GHz
RF
OUT
A+ = 5 GHz
RF
OUT
B = 10 GHz
RF
OUT
A+ = 1 GHz to 6.8 GHz
RF
OUT
B = 6.8 GHz to 13.6 GHz
RF
OUT
A+ = 1 GHz
RF
OUT
A+ = 6.8 GHz
RF
OUT
B = 6.8 GHz
RF
OUT
B = 13.6 GHz
VCO noise in open-loop conditions
Harmonic Content
Second
Third
Fundamental VCO Feedthrough
RF Output Power
4
Variation
Variation over Frequency
Level of Signal with RF Output
Disabled
−26
−29
−32
−14
−10
8
−1
0
2
±1
±1
±5
±3
−53
−20
−16
−12
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
−115
−135
−137
−155
−113
−133
−135
−153
−110
−130
−132
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
Rev. 0 | Page 4 of 38
Data Sheet
Parameter
VCO 2× Phase Noise Performance
Symbol
Min
Typ
−110
−130
−132
−149
−107
−127
−129
−147
−103
−124
−126
−144
Normalized In-Band Phase Noise
Floor
Fractional Channel
5
Integer Channel
6
Normalized 1/f Noise, PN
1_f7
Integrated RMS Jitter (1 kHz to
20 MHz)
8
Spurious Signals Due to PFD
Frequency
1
2
ADF5356
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
VCO noise in open-loop conditions
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
100 kHz offset from 10 GHz carrier
800 kHz offset from 10 GHz carrier
1 MHz offset from 10 GHz carrier
10 MHz offset from 10 GHz carrier
100 kHz offset from 13.6 GHz carrier
800 kHz offset from 13.6 GHz carrier
1 MHz offset from 13.6 GHz carrier
10 MHz offset from 13.6 GHz carrier
−225
−227
−121
97
−85
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
10 kHz offset; normalized to 1 GHz
V
CP
is the voltage at the CP
OUT
pin.
I
OL
is the output low current.
3
T
A
= 25°C; AV
DD
= DV
DD
= V
RF
= 3.3 V; V
VCO
= V
P
= 5.0 V; prescaler = 8/9; f
REFIN
= 122.88 MHz; f
PFD
= 61.44 MHz; and f
RF
= 1650 MHz.
4
RF output power using the
EV-ADF5356SD1Z
evaluation board is measured by a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins
are terminated into 50 Ω.
5
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−225 + 10log(f
PFD
) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−227 + 10log(f
PFD
) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF
)
and at a frequency offset (f) is given by PN = P
1_f
+ 10log(10 kHz/f) + 20log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL
design tool.
8
Integrated rms jitter using the
EV-ADF5356SD1Z
evaluation board is measured by a spectrum analyzer. The
EV-ADF5356SD1Z
evaluation board is configured to accept
a single-ended REF
IN
signal (SMA 100) = 160 MHz, VCO frequency = 6 GHz, f
PFD
= 80 MHz, charge pump current = 0.9 mA, with bleed current off. The loop filter is
configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated into 50 Ω.
Rev. 0 | Page 5 of 38
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