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XCV400E-6BG240C

Description
FPGA, 6144 CLBS, 331776 GATES, 357 MHz, PQFP240
Categorysemiconductor    Programmable logic devices   
File Size64KB,5 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XCV400E-6BG240C Overview

FPGA, 6144 CLBS, 331776 GATES, 357 MHz, PQFP240

XCV400E-6BG240C Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals240
Maximum operating temperature85 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage1.89 V
Minimum supply/operating voltage1.71 V
Rated supply voltage1.8 V
Processing package descriptionHQFP-240
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeFLATPACK, FINE PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.5000 mm
terminal coatingtin lead
Terminal locationFour
Packaging MaterialsPlastic/Epoxy
Temperature levelother
organize6144 CLBS, 331776 Door
Maximum FCLK clock frequency357 MHz
Number of configurable logic modules6144
Programmable logic typeFIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits331776
The maximum delay of a CLB module0.4700 ns
0
R
Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
Features
Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink™
Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port™ BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
* ZBT is a trademark of Integrated Device Technology, Inc.
High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for
million-plus gate density designs
- Wide selection of PC and workstation platforms
SRAM-Based In-System Configuration
- Unlimited re-programmability
Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
0.18
m
m 6-Layer Metal Process
100% Factory Tested
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
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