Data Sheet
FEATURES
16-/32-Channel, 4 Ω, +1.8 V to +5.5 V and
±2.5 V Analog Multiplexers
ADG726/ADG732
FUNCTIONAL BLOCK DIAGRAMS
ADG726
S1A
DA
S16A
A0 A1 A2 A3 EN
APPLICATIONS
Optical applications
Data acquisition systems
Communication systems
Relay replacement
Audio and video switching
Battery-powered systems
Medical instrumentation
Automatic test equipment (ATE)
S1
Figure 1.
ADG732
D
S32
WR
CS
1-OF-32
DECODER
02765-002
A0 A1 A2 A3 A4 EN
Figure 2.
GENERAL DESCRIPTION
The
ADG726/ADG732
are monolithic, complementary metal
oxide semiconductor (CMOS) 32-channel and dual 16-channel
analog multiplexers. The
ADG732
switches one of 32 inputs (S1
to S32) to a common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3, and A4. The
ADG726
switches one
of 16 inputs as determined by the 4-bit binary address lines A0,
A1, A2, and A3.
On-chip latches facilitate microprocessor interfacing. The
ADG726
may also be configured for differential operation by tying CSA
and CSB together. An EN input is used to enable or disable the
devices. When disabled, all channels are switched off.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a
±2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms and is
Rev. B
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closely matched between switches and very flat over the full signal
range. These devices can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends to
the supplies. In the off condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The
ADG726/ADG732
are available in a 48-lead LFCSP or a
48-lead TQFP. For functionally equivalent devices with serial
interface, see the
ADG725/ADG731.
PRODUCT HIGHLIGHTS
1.
+1.8 V to +5.5 V single- or ±2.5 V dual-supply operation.
These devices are specified and guaranteed with +5 V ± 10%,
+3 V ± 10% single-supply, and ±2.5 V ± 10% dual-supply rails.
An on resistance of 4 Ω.
Guaranteed break-before-make switching action.
48-lead LFCSP package or 48-lead TQFP package.
2.
3.
4.
02765-001
1.8 V to 5.5 V single-supply operation
±2.5 V dual-supply operation
On resistance: 4 Ω at 25°C (+5 V single supply/±2.5 V dual
supply)
0.5 Ω on-resistance flatness at 25°C (+5 V single supply/
±2.5 V dual supply)
Rail-to-rail operation
Transition times: 23 ns typical at 25°C
Single 32-to-1 channel multiplexer
Dual/differential 16-to-1 channel multiplexer
TTL-/CMOS-compatible inputs
48-lead TQFP or 48-lead, 7 mm × 7 mm LFCSP
S1B
DB
S16B
WR
CSA
CSB
1-OF-16
DECODER
ADG726/ADG732
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
+5 V Single Supply ....................................................................... 3
+3 V Single Supply ....................................................................... 5
±2.5 V Dual Supply ...................................................................... 7
Timing Characteristics ................................................................ 8
Data Sheet
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configurations and Function Description........................... 10
48-Lead TQFP ............................................................................ 10
48-Lead LFCSP ........................................................................... 12
Typical Performance Characteristics ........................................... 15
Test Circuits..................................................................................... 17
Terminology .................................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/15—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ................................................... 10
Added Figure 5 and Table 7; Renumbered Sequentially ........... 11
Added Figure 6 and Table 8........................................................... 12
Changes to Figure 7, Table 9, and Table 10 ................................. 13
Changes to Table 11 ........................................................................ 14
2/15—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 5 ............................................................................ 9
Added Table 6; Renumbered Sequentially .................................. 10
Added Table 7.................................................................................. 11
Changes to Figure 5 ........................................................................ 11
Changes to Figure 8 to Figure 11 .................................................. 13
Changes to Figure 13 and Figure 15 to Figure 17....................... 14
Changes to Figure 25 to Figure 28 ................................................ 16
Changes to Figure 29 ...................................................................... 17
Moved Terminology Section ......................................................... 18
Changes to Terminology Section.................................................. 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/02—Revision 0: Initial Version
Rev. B | Page 2 of 21
Data Sheet
SPECIFICATIONS
+5 V SINGLE SUPPLY
V
DD
= 5 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 1.
ADG726/ADG732
−40°C to
+25°C +85°C
0 V to V
DD
5
6
0.3
0.8
On Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
ADG726
ADG732
Channel On Leakage
ADG726
ADG732
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Low or High
Digital Input Capacitance
DYNAMIC CHARACTERISTICS
1
Transition Time
Break-Before-Make Time Delay
On Time (CS, WR)
Off Time (CS, WR)
On Time (EN)
Off Time (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG726
ADG732
R
FLAT (ON)
0.5
1
I
S
(Off )
I
D
(Off )
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
1.2
ADG732
−40°C to
+125°C
ADG726/ADG732
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
On Resistance Match Between
Channels
Symbol
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
MHz typ
Test Conditions/Comments
R
ON
ΔR
ON
4
5.5
V
S
= 0 V to V
DD
, I
DS
= 10 mA, see Figure 20
V
S
= 0 V to V
DD
, I
DS
= 10 mA
7
1
V
S
= 0 V to V
DD
, I
DS
= 10 mA
V
DD
= 5.5 V
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V, see Figure 21
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V, see Figure 24
±1
±2.5
±5
±2.5
±5
2.4
0.8
±2
±10
I
D
, I
S
(On)
V
D
= V
S
= 1 V, or 4.5 V, see Figure 25
±10
2.4
0.8
V
INH
V
INL
I
INL
or I
INH
C
IN
t
TRANSITION
t
D
t
ON
(CS, WR)
t
OFF
(CS, WR)
t
ON
(EN)
t
OFF
(EN)
Q
INJ
I
SO
C
TK
BW
0.005
V
IN
= V
INL
or V
INH
±0.5
5
23
34
18
18
25
17
23
24
32
16
22
5
−72
−72
34
18
±0.5
40
1
32
29
40
25
48
1
38.5
33
43
25
R
L
= 300 Ω, C
L
= 35 pF, see Figure 27
V
S1
= 3 V/0 V, V
S32
= 0 V/3 V
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 28
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 29
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 29
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 30
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 3 V, see Figure 30
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 22
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 23
R
L
= 50 Ω, C
L
= 5 pF, see Figure 26
Rev. B | Page 3 of 21
ADG726/ADG732
Parameter
Off Switch Source Capacitance
Off Switch Drain Capacitance
ADG726
ADG732
On Switch Drain, Source
Capacitance
ADG726
ADG732
POWER REQUIREMENTS
Positive Supply Current
1
Data Sheet
Symbol
C
S
(Off )
C
D
(Off )
ADG726/ADG732
−40°C to
+25°C +85°C
13
170
340
C
D
, C
S
(On)
175
350
I
DD
10
20
20
pF typ
pF typ
µA typ
µA max
f = 1 MHz
f = 1 MHz
V
DD
= 5.5 V
Digital inputs = 0 V or 5.5 V
ADG732
−40°C to
+125°C
Unit
pF typ
pF typ
pF typ
Test Conditions/Comments
f = 1 MHz
f = 1 MHz
f = 1 MHz
Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 21
Data Sheet
+3 V SINGLE SUPPLY
V
DD
= 3 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
ADG726/ADG732
−40°C to
+25°C +85°C
0 V to V
DD
R
ON
ΔR
ON
7
11
12
0.35
1
3
13
ADG732
−40°C to
+125°C
ADG726/ADG732
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
On Resistance Match Between
Channels
On Resistance Flatness
LEAKAGE CURRENTS
Source Off Leakage
Drain Off Leakage
ADG726
ADG732
Channel On Leakage
ADG726
ADG732
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Low or High
Digital Input Capacitance
DYNAMIC CHARACTERISTICS
1
Transition Time
Break-Before-Make Time Delay
On Time (CS, WR)
Off Time (CS, WR)
On Time (EN)
Off Time (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG726
ADG732
Symbol
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Test Conditions/Comments
V
S
= 0 V to V
DD
, I
DS
= 10 mA, see Figure 20
V
S
= 0 V to V
DD
, I
DS
= 10 mA
1
R
FLAT (ON)
V
S
= 0 V to V
DD
, I
DS
= 10 mA
V
DD
= 3.3 V
V
S
= 3 V/1 V, V
D
= 1 V/3 V, see Figure 21
V
S
= 1 V/3 V, V
D
= 3 V/1 V, see Figure 24
I
S
(Off )
I
D
(Off )
I
D
, I
S
(On)
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
±1
±2.5
±5
±2.5
±5
2.0
0.7
±2
±10
±10
2.0
0.7
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
MHz typ
V
S
= V
D
= 1 V or 3 V, see Figure 25
V
INH
V
INL
I
INL
or I
INH
C
IN
t
TRANSITION
t
D
t
ON
(WR, CS)
t
OFF
(WR, CS)
t
ON
(EN)
t
OFF
(EN)
Q
INJ
I
SO
C
TK
BW
0.005
V
IN
= V
INL
or V
INH
±0.5
5
34
52
26
29
43
26
38
33
48
19
25
1
−72
−72
34
18
±0.5
62
1
52
42
55
28
69
1
60
55.5
63.5
28
R
L
= 300 Ω, C
L
= 35 pF, see Figure 27
V
S1
= 2 V/0 V, V
S32
= 0 V/2 V
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 2 V, see Figure 28
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 2 V, see Figure 29
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 2 V, see Figure 29
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 2 V, see Figure 30
R
L
= 300 Ω, C
L
= 35 pF; V
S
= 2 V, see Figure 30
V
S
= 1.5 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 22
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 23
R
L
= 50 Ω, C
L
= 5 pF, see Figure 26
Rev. B | Page 5 of 21
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