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SIT3907AC-2F-33NE-24.000000T

Description
OSC DCXO 24.0000MHZ LVCMOS LVTTL
CategoryPassive components   
File Size419KB,10 Pages
ManufacturerSiTime
Environmental Compliance
Download Datasheet Parametric View All

SIT3907AC-2F-33NE-24.000000T Overview

OSC DCXO 24.0000MHZ LVCMOS LVTTL

SIT3907AC-2F-33NE-24.000000T Parametric

Parameter NameAttribute value
typeDCXO
frequency24MHz
Function-
outputLVCMOS,LVTTL
Voltage - Power3.3V
frequency stability±10ppm
Operating temperature-20°C ~ 70°C
Current - Power (maximum)34mA
grade-
Installation typesurface mount
Package/casing4-SMD, no leads
size/dimensions0.126" long x 0.098" wide (3.20mm x 2.50mm)
Height - Installation (maximum)0.032"(0.80mm)
Current - Power (disabled) (maximum)-
SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Factory programmable between 1 MHz and 220 MHz
Digitally controlled pull range: ±25, ±50, ±100, ±200, ±400, ±800,
±1600 PPM
Eliminate the need for an external DAC
Superior pull range linearity of <= 0.01%
LVCMOS/LVTTL compatible output
Three industry-standard packages: 3.2 mm x2.5 mm (4-pin), 5.0 mm
x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin)
Programmable drive strength to reduce EMI
Outstanding silicon reliability of 2 FIT
Ideal for clock synchronization, instrumentation, low
bandwidth PLL, jitter cleaner, clock recovery, audio,
video, and FPGA
Electrical Characteristics
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
F_aging
T_use
Min.
1
-10
-25
-50
Aging
Operating Temperature Range
-5
-20
-40
1.71
Supply Voltage
Vdd
2.25
2.52
2.97
Pull Range
Linearity
Frequency Change Polarity
Frequency Update Rate
Current Consumption
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Output Load
Start-up Time
Input Low Voltage
Input Middle Voltage
Input High Voltage
Input High or Low Logic Pulse
Input Middle Pulse Width
Input Impedance
Input Capacitance
RMS period Jitter
RMS Phase Jitter (random)
PR
Lin
F_update
Idd
DC
Tr, Tf
VOH
VOL
Ld
T_start
VIL
VIM
VIH
T_logic
T_middle
Zin
Cin
T_jitt
T_phj
45
90
0.4xVdd
0.8xVdd
500
500
100
Typ.
1.8
2.5
2.8
3.3
±400, ±800, ±1600
Positive Slope
32
31
1.2
6
5
1.5
2
0.6
0.65
25
12.5
34
34
55
2
10
15
10
0.2xVdd
0.6xVdd
2
3
1
1
0.01
Max.
220
+10
+25
+50
+5
+70
+85
1.89
2.75
3.08
3.63
Unit
MHz
PPM
PPM
PPM
PPM
°C
°C
V
V
V
V
PPM
%
kU / s
kU / s
mA
mA
%
ns
%Vdd
%Vdd
pF
ms
V
V
V
ns
ns
kΩ
pF
ps
ps
ps
ps
20% to 80%
f = 20 MHz, all Vdds
f = 20 MHz, all Vdds
f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdds. No activity on DP pin.
With full activity on DP pin.
See Figure 5
See Figure 5
See Figure 5
See Figure 5
See Figure 5
Frequency control mode 1, see Table 1
Frequency control mode 2, see Table 2
No load condition, f = 100 MHz, Vdd = 2.5V, 2.8V or 3.3V
No load condition, f = 100 MHz, Vdd = 1.8 V
Vdd = 1.8V, 2.5V, 2.8V or 3.3V
Vdd =1.8V, 2.5V, 2.8V or 3.3V, 10% - 90% Vdd level
IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
See the last page for Absolute Pull Range, APR table
10 years
Extended Commercial
Industrial
Inclusive of initial tolerance, operating temperature, rated
power, supply voltage and load change
Condition
±25, ±50, ±100, ±200
Notes:
1. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.
2. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
SiTime Corporation
Rev. 1.2
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised July 24, 2014
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