xTAG v3.0 Hardware Manual
I N TH I S D OCU MENT
Introduction
XS1-U8 device
xSYS Connector (J2)
J3 and J4 connectors
24MHz Crystal Oscillator
I/O Port-to-Pin Mapping
xTAG v3.0 Schematic
1 Introduction
The xTAG v3.0 debug adapter converts between an XMOS XSYS connector and USB
2.0, providing pins for JTAG control, system reset, processor debug, one duplex
UART link and one duplex serial XMOS Link. The xTAG v3.0 debug adapter can
be used to connect XMOS development kits to most PCs, and provide a 5V power
supply from a USB 2.0 port.
The diagram below shows the layout of the components on the card.
J3
J4
20-way
IDC xSYS
connector
Figure 1:
xTAG v3.0
features
J1
Standard
USB-B
connector
J2
LEDs
To debug a board with the xTAG v3.0 you must use xTIMEcomposer 13.1 or later,
available from the XMOS web site:
http://xmos.com/downloads
.
The board requires an XMOS xSYS connector.
Publication Date: 2015/6/1
XMOS © 2015, All Rights Reserved
Document Number: XM006125A
xTAG v3.0 Hardware Manual
2/8
2 XS1-U8 device
The xTAG v3.0 is based on a single XS1-U8 device in a BGA package. The XS1-U8
consists of a single xCORE, which comprises a multicore microcontroller with
tightly integrated general purpose I/O pins and 64 KBytes of on-chip RAM. The
pins are brought out of the package and connected to the card’s components as
follows:
USB Connector (J1) The xTAG v3.0 uses a Standard B-type micro USB connector
to link to a PC. The USB connector is connected to the XS1-U8 device.
xSYS 20-way IDC header
The processor has ports that are directly connected to the I/O pins. Six LEDs are
driven by the debugger, their function (clockwise, starting from the power button
on the bottom right):
Power
Run
Status
Green
Green
Red
Green
Red
Target
Green
The xTAG is powered on
Target is running
Target is in debug mode and stopped
Target stop reason is expected e.g. breakpoint,
print message
Target stop reason is unexpected e.g. exception
Target device is detected after a Run Configuration
or Debug Configuration is used (
xrun
or
xgdb
command)
Target device is not detected after a Run
Configuration or Debug Configuration is used
(
xrun
or
xgdb
command)
xSCOPE is enabled
No xSCOPE
There is JTAG activity with the target happening
No JTAG
Red
xSCOPE
JTAG
Green Flashing
Off
Green
Off
3 xSYS Connector (J2)
The xTAG v3.0 includes an xSYS 20-way IDC header, which can be used to connect
it to an XMOS development board for debugging programs on the hardware.
The xSYS connector provides pins for JTAG control, system reset, processor debug,
a duplex UART link and a 2-bit serial xCONNECT Link.
XM006125A
xTAG v3.0 Hardware Manual
3/8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal
5V
NC
MSEL
GND
TDSRC
XL1_UP1
TMS
GND
TCK
XL1_UP0
DEBUG
GND
TDSNK
XL1_DN0
RST_N
GND
UART_RX
XL1_DN1
UART_TX
GND
Direction
Target to Host
N/A
Host to Target
N/A
Host to Target
Target to Host
Host to Target
N/A
Host to Target
Target to Host
Bidirectional
N/A
Target to Host
Host to Target
Host to Target
N/A
Host to Target
Host to Target
Target to Host
N/A
Description
Power
No connection
Select boot from JTAG - Active Low
Ground
JTAG Test Data
xCONNECT Link
JTAG Test Mode Select
Ground
JTAG Test Clock
xCONNECT Link
Debug
Ground
JTAG Test Data
xCONNECT Link
System Reset - Active Low
Ground
Serial Port
xCONNECT Link
Serial Port
Ground
The routing of these I/O pins along with the power pins is shown below.
3.1
xCONNECT Link configuration
Some of the I/O pins on the processor are configured as a duplex 2-bit serial
xCONNECT Link. The mapping of xCONNECT Link to the pins is shown in the table
below:
XM006125A
xTAG v3.0 Hardware Manual
4/8
1
5V
MSEL
TDSCR
TMS
TCK
DEBUG
TDSNK
RST_N
UART_RX
UART_TX
2
NC
GND
XL1_UP1
GND
XL1-_UP0
GND
XL1-DN0
GND
XL1-DN1
GND
Figure 2:
xTAG v3.0
xSYS pinout
19 20
Pin
X0D52
X0D53
X0D54
X0D55
xCONNECT Link
XL1_UP1
XL1_UP0
XL1_DN0
XL1_DN1
3.2 JTAG Configuration
Some of the I/O pins on the microcontroller are driven by the JTAG signals. The
mapping of the signals to the pins is shown in the table below:
Pin
X0D11
X0D13
X0D22
X0D10
X0D70
Port
P1D0
P1F0
P1G0
P1C0
P32A19
Processor
TDSRC
TDSNK
TMS
TCK
MSEL
XM006125A
xTAG v3.0 Hardware Manual
5/8
3.3 System Reset
The system reset signal is mapped to a 1-bit port on the processor as described
below. It is used as an output to reset the target processor from the debugger
Pin
X0D50
Port
P32A1
Processor
RST_N
4 J3 and J4 connectors
The xTAG v3.0 has two additional connectors. These are reserved for future use.
5 24MHz Crystal Oscillator
The XS1-U8 is clocked at 24MHz by a crystal oscillator on the card. The processor
is clocked at 500MHz and the I/O ports at 100MHz, by an on-chip phase locked
loop (PLL).
XM006125A
京公网安备 11010802033920号
EEWORLD
