Blackfin
Embedded Processor
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See
Operating Conditions
on Page 22
Qualified for Automotive Applications. See
Automotive
Products on Page 67
168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518/ADSP-BF518F16 only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I
2
S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Optional 16M bit SPI flash with boot option
Flexible booting options from internal SPI flash, OTP
memory, external SPI/parallel memories, or from SPI/UART
host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection
RTC
OTP
WATCHDOG TIMER
PERIPHERAL
ACCESS BUS
COUNTER
JTAG TEST AND EMULATION
3-PHASE PWM
TIMER7–0
B
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
16
EXTERNAL ACCESS BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
INTERRUPT
CONTROLLER
TWI
SPORT1-0
RSI (SDIO)
PORTS
DMA
CONTROLLER
DMA
EXTERNAL
BUS
BOOT
ROM
16M bit SPI Flash
(See Table 1)
PPI
UART1–0
DMA CORE BUS
EMAC
SPI1
SPI0
Figure 1. Functional Block Diagram
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Rev. D
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ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 5
Event Handling .................................................... 7
DMA Controllers .................................................. 8
Processor Peripherals ............................................. 8
Dynamic Power Management ................................ 12
Voltage Regulation Interface .................................. 14
Clock Signals ..................................................... 14
Booting Modes ................................................... 15
Instruction Set Description ................................... 16
Development Tools ............................................. 16
Additional Information ........................................ 18
Related Signal Chains .......................................... 18
Lockbox Secure Technology Disclaimer ................... 18
Signal Descriptions ................................................. 19
Specifications ........................................................ 22
Operating Conditions ........................................... 22
Electrical Characteristics ....................................... 24
Flash Memory Characteristics ................................ 26
Absolute Maximum Ratings ................................... 27
Package Information ............................................ 28
ESD Sensitivity ................................................... 28
Timing Specifications ........................................... 29
Output Drive Currents ......................................... 52
Test Conditions .................................................. 54
Thermal Characteristics ........................................ 58
176-Lead LQFP_EP Lead Assignment ......................... 59
168-Ball CSP_BGA Ball Assignment ........................... 62
Outline Dimensions ................................................ 65
Surface-Mount Design .......................................... 66
Automotive Products .............................................. 67
Ordering Guide ..................................................... 67
REVISION HISTORY
4/14—Rev. C to Rev. D
This Rev D product data sheet includes Flash memory specifica-
tions that differ from all previous data sheet versions (A, B, C).
The Flash memory specifications contained in the Rev D prod-
uct data sheet are appropriate only for those products that
include 16M bit SPI Flash memory.
These changes are reflected in the following sections:
Processor Comparison .............................................. 3
Flash Memory ......................................................... 5
Operating Conditions ............................................. 22
Electrical Characteristics .......................................... 24
Flash Memory Characteristics ................................... 26
Ordering Guide ..................................................... 67
Rev. D | Page 2 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF514/ADSP-BF514F16/ADSP-
BF516/ADSP-BF518/ADSP-BF518F16 processors are members
of the Blackfin
®
family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-
cessors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like micro-
processor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction-set
architecture.
The processors are completely code compatible with other
Blackfin processors.
Table 1. Processor Comparison
ADSP-BF514F16
ADSP-BF518F16
ADSP-BF512
ADSP-BF514
ADSP-BF516
ADSP-BF518
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF51x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, cost-
effective applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC with
IEEE-1588 support (ADSP-BF518/ADSP-BF518F16 only), an
RSI controller, a TWI controller, two UART ports, two SPI
ports, two serial ports (SPORTs), nine general-purpose 32-bit
timers (eight with PWM capability), 3-phase PWM for motor
control, a real-time clock, a watchdog timer, and a parallel
peripheral interface (PPI).
Feature
IEEE-1588
Ethernet MAC
RSI
TWI
SPORTs
UARTs
SPIs
GP Timers
Watchdog Timers
RTC
PPI
Flash (M bit)
Rotary Counter
3-Phase PWM Pairs
GPIOs
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
Maximum Speed Grade
Package Options
Memory (bytes)
–
–
–
1
2
2
2
8
1
1
1
–
1
3
40
–
–
1
1
–
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
16 –
– 16
1
1
1
1
3
3
3
3
40 40 40 40
32K
16K
32K
32K
4K
32K
400 MHz
176-Lead LQFP_EP (with
Exposed Pad)
168-Ball CSP_BGA
–
–
1
1
2
2
2
8
1
1
1
–
1
3
40
BLACKFIN PROCESSOR CORE
As shown in
Figure 2,
the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. D | Page 3 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1
DA0
TO MEMORY
32
32
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD
LD1
LD0
32
32
32
32
32
ASTAT
SEQUENCER
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
16
8
8
8
16
8
DECODE
ALIGN
40
40
40
40
LOOP BUFFER
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit
Rev. D | Page 4 of 68 | April 2014
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. The memory map for both internal and exter-
nal memory space is shown in
Figure 3.
Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip
memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION BANK C SRAM/CACHE (16K BYTES)
0xFFA1 0000
RESERVED
0xFFA0 8000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 4000
INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTES)
0xFF90 4000
DATA BANK B SRAM (16K BYTES)
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTES)
0xFF80 4000
DATA BANK A SRAM (16K BYTES)
0xFF80 0000
RESERVED
0xEF00 8000
BOOT ROM (32K BYTES)
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
0x2000 0000
0x08 00 0000
0x0000 0000
RESERVED
SDRAM MEMORY (16M BYTES - 128M BYTES)
External (Off-Chip) Memory
INTERNAL MEMORY MAP
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank, and the SDRAM controller supports up
to four internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
EXTERNAL MEMORY MAP
0xEF00 0000
Flash Memory
The ADSP-BF51xF processors contain an SPI flash memory
within the package of the processor connected to SPI0
(Figure
4).
The SPI flash memory has a 16M bit capacity. Also included are
support for software write protection and for fast erase and
byte-program.
Figure 3. ADSP-BF51x Internal/External Memory Map
Rev. D | Page 5 of 68 | April 2014
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