DIGITAL AUDIO CORE ................................................................................................................................................................................................. 45
DIGITAL INTERFACES ................................................................................................................................................................................................. 45
OTHER FEATURES ...................................................................................................................................................................................................... 45
ANALOGUE LINE INPUT .............................................................................................................................................................................................. 50
DIGITAL MICROPHONE INPUT.................................................................................................................................................................................... 50
INPUT SIGNAL PATH ENABLE .................................................................................................................................................................................... 52
INPUT SIGNAL PATH SAMPLE RATE CONTROL ....................................................................................................................................................... 53
INPUT SIGNAL PATH CONFIGURATION .................................................................................................................................................................... 54
INPUT SIGNAL PATH DIGITAL VOLUME CONTROL .................................................................................................................................................. 61
INPUT SIGNAL PATH ANC CONTROL ........................................................................................................................................................................ 67
DIGITAL MICROPHONE PIN CONFIGURATION ......................................................................................................................................................... 67
DIGITAL CORE MIXERS ............................................................................................................................................................................................... 70
DIGITAL CORE INPUTS................................................................................................................................................................................................ 74
DIGITAL CORE OUTPUT MIXERS ............................................................................................................................................................................... 75
DYNAMIC RANGE CONTROL (DRC) ........................................................................................................................................................................... 82
LOW PASS / HIGH PASS DIGITAL FILTER (LHPF) ..................................................................................................................................................... 94
DIGITAL CORE DSP ..................................................................................................................................................................................................... 96
TONE GENERATOR ..................................................................................................................................................................................................... 99
HAPTIC SIGNAL GENERATOR .................................................................................................................................................................................. 101
SAMPLE RATE CONTROL ......................................................................................................................................................................................... 106
DSP DIRECT MEMORY ACCESS (DMA) CONTROL ................................................................................................................................................ 134
GENERAL PURPOSE TIMERS ................................................................................................................................................................................... 155
MASTER AND SLAVE MODE OPERATION ............................................................................................................................................................... 167
AUDIO DATA FORMATS............................................................................................................................................................................................. 167
TDM OPERATION BETWEEN THREE OR MORE DEVICES .................................................................................................................................... 171
AIF MASTER / SLAVE CONTROL .............................................................................................................................................................................. 174
AIF SIGNAL PATH ENABLE........................................................................................................................................................................................ 177
AIF BCLK AND LRCLK CONTROL ............................................................................................................................................................................. 180
AIF DIGITAL AUDIO DATA CONTROL ....................................................................................................................................................................... 185
AIF TDM AND TRI-STATE CONTROL ........................................................................................................................................................................ 189
CONTROL SPACE ...................................................................................................................................................................................................... 191
DATA SPACE .............................................................................................................................................................................................................. 192
INFORMATION MANAGEMENT ................................................................................................................................................................................. 193
VALUE MANAGEMENT (INCLUDING REGISTER ACCESS) .................................................................................................................................... 194
DATA CHANNEL CONFIGURATION .......................................................................................................................................................................... 194
SLIMBUS MESSAGE SUPPORT ................................................................................................................................................................................ 195
SLIMBUS PORT NUMBER CONTROL ....................................................................................................................................................................... 198
SLIMBUS SIGNAL PATH ENABLE ............................................................................................................................................................................. 199
SLIMBUS CONTROL REGISTER ACCESS ............................................................................................................................................................... 200
SLIMBUS CLOCKING CONTROL ............................................................................................................................................................................... 202
OUTPUT SIGNAL PATH ENABLE .............................................................................................................................................................................. 206
OUTPUT SIGNAL PATH SAMPLE RATE CONTROL ................................................................................................................................................. 208
OUTPUT SIGNAL PATH CONTROL ........................................................................................................................................................................... 208
OUTPUT SIGNAL PATH DIGITAL FILTER CONTROL .............................................................................................................................................. 210
OUTPUT SIGNAL PATH DIGITAL VOLUME CONTROL ............................................................................................................................................ 212
4
Rev 4.2
CS47L85
OUTPUT SIGNAL PATH NOISE GATE CONTROL .................................................................................................................................................... 218
OUTPUT SIGNAL PATH AEC LOOPBACK ................................................................................................................................................................ 220
HEADPHONE OUTPUTS AND MONO MODE ........................................................................................................................................................... 221
JACK DETECT............................................................................................................................................................................................................. 227
JACK POP SUPPRESSION (MICDET CLAMP AND GP SWITCH) ............................................................................................................................ 229
CONTROL SEQUENCE FOR JACK DETECT & MICDET CLAMP ............................................................................................................................ 232
GPIO FUNCTION SELECT.......................................................................................................................................................................................... 247
PIN-SPECIFIC ALTERNATIVE FUNCTION ................................................................................................................................................................ 250
INTERRUPT (IRQ) STATUS OUTPUT ........................................................................................................................................................................ 251
FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT ............................................................................................................................................. 252
FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ........................................................................................................................................... 253
OPCLK AND OPCLK_ASYNC CLOCK OUTPUT ....................................................................................................................................................... 253
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT ......................................................................................................................................... 254
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT ............................................................................................. 255
OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT ....................................................... 255
GENERAL PURPOSE TIMER STATUS OUTPUT ...................................................................................................................................................... 255
EVENT LOGGER FIFO BUFFER STATUS OUTPUT ................................................................................................................................................. 256
GENERAL PURPOSE SWITCH .................................................................................................................................................................................. 256
SYSTEM CLOCKING................................................................................................................................................................................................... 287
SAMPLE RATE CONTROL ......................................................................................................................................................................................... 287
SYSCLK AND ASYNCCLK CONTROL ....................................................................................................................................................................... 289
DSPCLK CONTROL .................................................................................................................................................................................................... 291
BCLK AND LRCLK CONTROL .................................................................................................................................................................................... 300
CONTROL INTERFACE CLOCKING .......................................................................................................................................................................... 300
FREQUENCY LOCKED LOOP (FLL) .......................................................................................................................................................................... 301
SPREAD SPECTRUM FLL CONTROL ....................................................................................................................................................................... 314
FLL INTERRUPTS AND GPIO OUTPUT..................................................................................................................................................................... 316
EXAMPLE FLL CALCULATION ................................................................................................................................................................................... 316
EXAMPLE FLL SETTINGS .......................................................................................................................................................................................... 317
INITIATING A SEQUENCE .......................................................................................................................................................................................... 324
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Embedded System
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