1.2 A, DC-to-DC Inverting Regulator
Data Sheet
FEATURES
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to V
IN
− 39 V
Integrated 1.2 A main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
Power-good output
UVLO, OCP, OVP, and TSD protection
3 mm × 3 mm, 16-lead LFCSP
−40°C to +125°C junction temperature
Supported by the
ADIsimPower
tool set
ADP5073
TYPICAL APPLICATION CIRCUIT
C
VREF
AVIN
V
IN
C
IN
PVIN
VREF
R
FB
ADP5073
ON
OFF
FB
R
FT
EN
SW
VREG
L1
D1
SS
PWRGD
COMP
SLEW
SYNC/FREQ
GND
C
OUT
C
VREG
V
OUT
R
PG
PWRGD
C
C
APPLICATIONS
Bipolar amplifiers, ADCs, digital-to-analog converters
(DACs), and multiplexers
High speed converters
Radio frequency (RF) power amplifier (PA) bias
Optical modules
Figure 1.
GENERAL DESCRIPTION
The
ADP5073
is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the
input voltage.
The
ADP5073
operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The
ADP5073
can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The
ADP5073
includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown. A power-good pin is
available to indicate the output is stable.
Other key safety features in the
ADP5073
include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The
ADP5073
is available in a 16-lead LFCSP and is rated for a
−40°C to +125°C operating junction temperature range.
Table 1. Related Devices
Device
ADP5070
ADP5071
ADP5073
ADP5074
ADP5075
Boost
Switch (A)
1.0
2.0
Not
applicable
Not
applicable
Not
applicable
Inverter
Switch (A)
0.6
1.2
1.2
2.4
0.8
Package
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
16-lead LFCSP (3 mm ×
3 mm)
16-lead LFCSP (3 mm ×
3 mm)
12-ball WLCSP
(1.61 mm × 2.18 mm)
Rev. A
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12817-001
R
C
ADP5073
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
PWM Mode ................................................................................. 10
Skip Mode .................................................................................... 10
Undervoltage Lockout (UVLO) ............................................... 10
Oscillator and Synchronization ................................................ 10
Data Sheet
Internal Regulators ..................................................................... 10
Precision Enabling...................................................................... 11
Soft Start ...................................................................................... 11
Slew Rate Control ....................................................................... 11
Current-Limit Protection ............................................................ 11
Overvoltage Protection .............................................................. 11
Power Good ................................................................................ 11
Thermal Shutdown .................................................................... 11
Applications Information .............................................................. 12
ADIsimPower Design Tool ....................................................... 12
Component Selection ................................................................ 12
Common Applications .............................................................. 15
Layout Considerations ............................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
10/2017—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
10/2015—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
SPECIFICATIONS
ADP5073
PVIN = AVIN = 2.85 V to 15 V, V
OUT
= −15 V, f
SW
= 1200 kHz, T
J
= −40°C to +125°C for minimum/maximum specifications, and
T
A
= 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total)
Shutdown Current
UVLO
System UVLO Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
SYNC/FREQ Input
Input Clock Range
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
PRECISION ENABLING (EN)
High Level Threshold
Low Level Threshold
Shutdown Mode
Pull-Down Resistance
INTERNAL REGULATOR
VREG Output Voltage
INVERTING REGULATOR
Reference Voltage
Accuracy
Feedback Voltage
Accuracy
Feedback Bias Current
Overvoltage Protection Threshold
Power-Good Threshold
Power-Good FET On Resistance
Power-Good FET Maximum Drain Source
Voltage
Power-Good Supply Voltage
Load Regulation
Line Regulation
Symbol
V
IN
Min
2.85
Typ
Max
15
Unit
V
Test Conditions/Comments
PVIN, AVIN
I
Q
I
SHDN
1.8
5
4.0
10
mA
µA
No switching, EN = high, PVIN = AVIN =
5V
No switching, EN = low, PVIN = AVIN =
5 V, −40°C ≤ T
J
≤ +85°C
AVIN
V
UVLO_RISING
V
UVLO_FALLING
V
HYS
f
SW
2.5
2.8
2.55
0.25
1.200
2.400
2.85
V
V
V
MHz
MHz
MHz
ns
ns
V
V
V
V
V
MΩ
V
V
%
%
V
%
%
µA
V
V
V
Ω
V
SYNC/FREQ = low
SYNC/FREQ = high (connect to VREG)
1.130
2.240
1.000
100
100
0.4
1.125
1.025
0.4
1.270
2.560
2.600
f
SYNC
t
SYNC_MIN_ON
t
SYNC_MIN_OFF
V
H (SYNC)
V
L (SYNC)
V
TH_H
V
TH_L
V
TH_S
R
EN
V
REG
V
REF
1.3
1.15
1.05
1.48
4.25
1.60
1.175
1.075
Internal circuitry disabled to achieve I
SHDN
−0.5
−1.5
V
REF
− V
FB
−0.5
−1.5
I
FB
V
OV
V
PG (GOOD)
V
PG (BAD)
R
DS_PG (ON)
V
DS_PG (MAX)
V
PG (SUPPLY)
∆(V
REF
− V
FB
)/
∆I
LOAD
∆(V
REF
− V
FB
)/
∆V
IN
0.74
0.7
0.68
28
0.8
+0.5
+1.5
+0.5
+1.5
0.1
T
J
= 25°C
T
J
= −40°C to +125°C
T
J
= 25°C
T
J
= −40°C to +125°C
At the FB pin after soft start is complete
V
REF
− V
FB
≥ V
PG (GOOD)
V
REF
− V
FB
≤ V
PG (BAD)
5.5
1.4
0.0025
0.02
Rev. A | Page 3 of 17
%/A
%/V
Voltage required on PVIN pin for power-
good FET to pull down
I
LOAD
= 100 mA to 500 mA (regulator
not in skip mode)
V
IN
= 2.85 V to 14.5 V, I
LOAD
= 15 mA
(regulator not in skip mode_
ADP5073
Parameter
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage
Current-Limit Threshold
Minimum On Time
Minimum Off Time
SOFT START
Soft Start Timer
Hiccup Time
THERMAL SHUTDOWN
Threshold
Hysteresis
Symbol
g
M
R
DS (ON)
V
DS (MAX)
I
LIM
Min
270
Typ
300
200
1.375
55
50
4
32
8 × t
SS
150
15
Max
330
39
1.6
Unit
µA/V
mΩ
V
A
ns
ns
ms
ms
ms
°C
°C
V
IN
= 5 V
Data Sheet
Test Conditions/Comments
1.2
t
SS
t
HICCUP
T
SHDN
T
HYS
SS = open
SS resistor = 50 kΩ to GND
Rev. A | Page 4 of 17
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
PVIN, AVIN
SW
GND
VREG
EN, FB, SYNC/FREQ, PWRGD
COMP, SLEW, SS, VREF
Operating Junction
Temperature Range
Storage Temperature
Range
Soldering Conditions
Rating
−0.3 V to +18 V
PVIN − 40 V to PVIN + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of AVIN + 0.3 V or +6 V
−0.3 V to +6 V
−0.3 V to VREG + 0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
ADP5073
THERMAL RESISTANCE
θ
JA
and Ψ
JT
are based on a 4-layer printed circuit board (PCB)
(two signals and two power planes) with thermal vias connecting
the exposed pad to a ground plane as recommended in the
Layout Considerations section. θ
JC
is measured at the top of the
package and is independent of the PCB. The Ψ
JT
value is more
appropriate for calculating junction to case temperature in the
application.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP
θ
JA
75.01
θ
JC
55.79
Ψ
JT
0.95
Unit
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 17
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