DEMO MANUAL DC200
HIGH SPEED ADC
LTC1416 (400ksps) and
LTC1419 (800ksps) 14-Bit
A/D Converter Demo Board
DESCRIPTIO
The LTC
®
1416/LTC1419 are, respectively, 2µs, 400ksps
and 1µs, 800 ksps sampling A/D converters. The LTC1416
draws 70mW and the LTC1419 draws 150mW. The
LTC1416/LTC1419 demo board provides the user with a
way to evaluate the LTC1416 and LTC1419 high speed
A/D converters. In addition, the LTC1416/LTC1419 demo
board is intended to illustrate the layout and bypassing
techniques required to obtain optimum performance from
these parts. The LTC1416/LTC1419 demo board is de-
signed to be easy to use and requires only
±7V
to
±15V
supplies, a conversion-start signal and an analog input
signal (single-ended or differential). As shown in the
Board Photo, the LTC1416/LTC1419 are very space effi-
cient solutions for A/D users. By combining a 14-bit A/D,
sample-and-hold and reference into a single SSOP pack-
age, all the data acquisition circuitry, including the bypass
capacitors, can be placed in an area of only 0.5 inch
2
.
This manual describes how to use the demo board.
Included are timing diagrams, power supply requirements
and analog input range information. Additionally, a sche-
TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTO
4096 Point FFT of LTC1419 Demo Board
0
–10
–20
–30
MAGNITUDE (dB)
–40
–50
–60
–70
–80
–90
–100
–110
0
100
200
300
400
FREQUENCY (kHz)
500
600
DC200 TA01
U
U W
U
matic, parts list, drawings and dimensions of all the PC
board layers are included. An explanation of the layout and
bypass strategies used in this board is also included, so
that anyone designing a PC board using the LTC1416/
LTC1419 will be able to get the maximum performance
from the device. The LTC1416/LTC1419 are intended for
applications in telecommunications, digital signal pro-
cessing, imaging, or any high speed, high resolution data
acquisition application.
Gerber files for this circuit board
are available. Call the LTC factory.
Some key features of this demo board include:
• Proven 400ksps (LTC1416) and 800ksps (LTC1419)
14-bit ADC surface mount layout
• Actual ADC footprint is only 0.5 inch
2
including
bypass capacitors
• 80dB SINAD and 90dB THD at 200kHz (LTC1416) and
80dB SINAD and 86dB THD at 400kHz (LTC1419)
inputs
, LTC and LT are registered trademarks of Linear Technology Corporation.
Component Side
DC200 BdPhoto
1
U2
24 CS
23 CONVST
22 RD
21 SHDN
20 B0
D01
D02
D03
D04
D05
D06
D07
U5
74HC574
1
B[00:13]
B00
B01
V
SS
1
2
3
4
25
24
23
22
21
28
27
26
V
CC
14
DGND
AGND
V
SS
5
V
SS
D1
D0
D2
DV
DD
D3
AV
DD
D4
17 B03
18 B02
19 B01
20 B00
SHDN
16 B04
D5
RD
15 B05
B12
B11
B10
B09
B08
B07
B06
D6
CONVST
13 B06
D7
CS
12 B07
1
11
2
3
4
5
6
7
8
9
DATA READY
V
LOGIC
5
14
U7F
C15
0.1µF
13
HC14
7
V
CC
U7G
HC14
GND
12
HC14
U7C
6
R21
1k
U7D
9
HC14
C16
15pF
8
D8
BUSY
11 B08
D9
REFCOMP
10 B09
D10
V
REF
9
B10
B13
D11
A
IN–
D12
8
B11
B05
A
IN+
D13
7
B12
B04
6
B13
B03
5
6
7
8
9
C3
0.1µF
B02
4
D1
D2
D3
D4
D5
D6
D7
U4
LTC1419/LTC1416
3
D0
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
U6
74HC574
0E
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
D12
D11
D10
D09
D08
D07
D06
11
HC14
U7E
10
D13
11
0E
19
18
17
16
15
14
13
12
D00
D01
D02
D03
D04
D05
D13
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
J6-13
J6-14
J6-11
J6-12
J6-9
J6-10
J6-7
J6-8
J6-5
J6-6
J6-3
J6-4
J6-1
J6-2
J6-15
J6-16
J6-17
J6-18
D12
D13
D08
D09
D10
D11
19 B1
18 B2
17 B3
16 B4
15 B5
D00
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
D[00:13]
R0 1.2k
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
LTC1416CG
LTC1419CG
–V
IN
AGND 5
B13 6
C1
22µF
10V
B10 9
B9 10
B8 11
B7 12
V
CC
G PACKAGE
28-LEAD PLASTIC SSOP
C4
0.1µF
B6 13
DGND 14
B12 7
B11 8
LT1121-5
HIGH SPEED ADC
+V
IN
J3
7V TO
15V
V
CC
V
CC
R14
20Ω
C12
0.1µF
C14
0.1µF
V
LOGIC
V
SS
25 BUSY
1
V
IN
V
OUT
3
J1
–7V TO
–15V 2
GND TABGND
2
4
C2
22µF
10V
C10
10µF
10V
J2
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
LED
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
DGND
DGND
HEADER
18-PIN
DM124 SCHEM
GND
DEMO MANUAL DC200
AGND
JP3
V
OUT
DGND
J4
V+
2
3
+
V– 4
1
8
JP2
R15
51Ω
U3
®
7 LT 1363
–
6
A
+
R17
10k
C11
1000pF
PACKAGE AND SCHEMATIC DIAGRAMS
R18
10k
A
–
R16
51Ω
J5
C8
1µF
10V
C13
22µF
10V
JP1
J7
U7A
U7B
CLK
1
2
3
4
R19
51Ω
HC14
HC14
V
LOGIC
C9
10µF
10V
C5
10µF
10V
JP5C
CS
JP5B
RD
JP5A
SHDN
R20
1M
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5%
2. ALL CAPACITOR VALUES IN
µF,
25V, 20% AND IN pF, 50V, 10%
3. THIS DEMO CIRCUIT IS AVAILABLE IN A LOW POWER
VERSION LTC1416, DEMO NUMBER DC200A-L
W
JP4
W
D02
+
D15
SS12
+
+
U1
79L05
1
IN
OUT
GND
5
D14
SS12
D00
D01
U
2
TOP VIEW
A
IN
1
27 DV
DD
26 V
SS
28 +AV
DD
A
IN
2
V
REF
3
REFCOMP 4
–
+
LTC1416/LTC1419 Demonstration Board Features Analog Input Signal Buffer, 400ksps/800ksps, Parallel Data Output 14-bit ADC,
Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 18-Pin Header, J6
DEMO MANUAL DC200
HIGH SPEED ADC
PARTS LIST
REFERENCE
DESIGNATOR
C1, C2
C3, C4, C12, C14, C15
C5, C9
C8
C10
C11
C13
C16
D0 to D13
D14, D15
J1, J2, J3
J4, J5, J7
J6
JP1
JP2, JP3, JP4
JP5
R0 to R13
R14
R15, R16
R17, R18
R19
R20
R21
U1
U2
U3
U4
U5, U6
U7
QUANTITY
2
5
2
1
1
1
1
1
14
2
3
3
1
1
3
1
14
1
2
2
1
1
1
1
1
1
1
2
1
4
4
4
PART NUMBER
TAJC226M010R
08053C104MAT1A
1206ZG106ZAT1A
0603ZG105ZAT1A
TAJB106M010R
06033A102KAT1A
1210ZG226ZAT1A
08055A150KAT1A
LN1251C-(TR)
SS12-PKG11
575-4
112404
PZC09DFAN
PZC02SAAN
JL-100-25-T
PZC03DFAN
CR10-122JM
CR10-200JM
RR0816Q510D
CR10-103JM
CR10-510JM
CR10-105JM
CR10-102JM
MC79L05ACDR1
LT1121CST-5
LT1363CS8
LTC1416CG
MC74HC574ADW
MC74HC14AD
SSC02SYAN
1902C
DESCRIPTION
22uF 10V 20% Tantalum Capacitor
0.1uF 25V 20% X7R Capacitor
10uF 10V Y5V Capacitor
1uF 10V Y5V Capacitor
10uF 10V 20% Tantalum Capacitor
1000pF 25V 10% NPO Capacitor
22uF 10V Y5V Capacitor
15pF 50V 10% NPO Capacitor
2.1V 15mA Red SMT LED
20V 1A SMA Schottky Diode
Standard Banana Jack Connector
50Ω BNC, PCB-Vertical Connector
18-Pin 2-Row 0.100cc Header Connector
2-Pin 0.100cc 0.025sq Jumper
0.100cc 22-AWG Wire Jumper
6-Pin 2-Row 0.100cc 0.025sq Jumper
1.2k 1/10W 5% Chip Resistor
20Ω 1/10W 5% Chip Resistor
51Ω 1/16W 0.5% Thin Film Chip Resistor
10k 1/10W 5% Chip Resistor
51Ω 1/10W 5% Chip Resistor
1M 1/10W 5% Chip Resistor
1k 1/10W 5% Chip Resistor
79L05 –5V SO-8 Regulator IC
5V SOT-224 Regulator IC
SO-8 Op Amp IC
SSOP-28 14-Bit ADC IC
SOL-20 Flip-Flop Octal D IC
SO-14 Hex-Inv Schmitt IC
0.100cc Shunt
#4-40 1/4" Screw
Nylon Hex #4-40 1/2" Standoff
VENDOR
AVX
AVX
AVX
AVX
AVX
AVX
AVX
AVX
Panasonic
General Inst
Keystone
Connex
Sullins
Sullins
Samtec
Sullins
TAD
TAD
Thin Film Tech
TAD
TAD
TAD
TAD
Motorola
LTC
LTC
LTC
Motorola
Motorola
Sullins
Any
Keystone
TELEPHONE
207-282-5111
803-946-0362
803-946-0362
803-946-0362
207-282-5111
803-946-0362
803-946-0362
803-946-0362
201-348-5217
516-847-3000
718-956-8900
805-378-6464
760-744-0125
760-744-0125
800-726-8329
760-744-0125
714-255-9123
714-255-9123
507-625-8445
714-255-9123
714-255-9123
714-255-9123
714-255-9123
602-655-3005
408-432-1900
408-432-1900
408-432-1900
602-655-3005
602-655-3005
800-726-8329
718-956-8900
QUICK START GUIDE
This demonstration board is easily set up for evaluating
the LTC1416/LTC1419. Follow the procedure below for
proper operation.
1. Connect a –7V to –15V supply (J1), 7V to 15V supply
(J3), 0V or ground (J2), input test signal generator
(J4) and conversion clock source (J7) to the board as
shown in Figure 1. As delivered, the board is config-
ured for a
±2.5V
input referenced to ground (JP2 and
JP4 are shorted). Differential inputs can be converted
by removing the shorting connector on JP4. The
demonstration board also includes an LT1363 input
buffer amplifier operating with a gain of 1. The input
signal can be buffered by removing the shorting
connector from JP2 and placing it on JP3.
2. The LTC1416/LTC1419 demo board includes an input
filter with a cutoff frequency of 1.56MHz. For lower
input frequencies, best results are obtained by using
an optional filter. The TTE J3449-100k-500-20 is a
3
DEMO MANUAL DC200
HIGH SPEED ADC
QUICK START GUIDE
100kHz lowpass filter and works well for frequencies
below 100kHz. At the Nyquist frequency of 200kHz,
the TTE LE1182T-200k-400-720B 200kHz lowpass or
TTE Q70T-200k-30k-400-720B 200kHz bandpass
filters work well. The signal generator and filter should
produce < – 96dB THD.
3. Adjust the magnitude of the input signal to within
10mV of negative and positive full scale. This ensures
that the maximum SINAD is achieved without the risk
of overdriving the input and producing unwanted
distortion. The conversion clock frequency can be set
within the range of 0kHz to 400kHz.
4. The conversion results can be observed in several
ways. The onboard LEDs indicate the state of each
data bit. This is useful for giving a preliminary indica-
tion that the conversions are taking place and verifying
results when converting DC signals. The 14-bit paral-
lel output data is available on header J6. This allows
monitoring of each bit and can be connected to a logic
analyzer, DSP or oscilloscope. The data format is
two’s complement. Offset binary format is also avail-
able by using D13 instead of D13.
5. Dynamic performance can be measured by using an
FFT-based analyzer. By synchronizing the analog in-
put signal’s frequency to the conversion rate, or using
a windowing function, accurate SINAD, THD or other
dynamic characteristics can be evaluated.
OPERATIO
OPERATING THE BOARD
Powering the Board
To use the demo board, apply
±7V
to
±15V
at 200mA to
the banana jacks J1 and J3, and 0V (GND) to J2. Be careful
to observe the correct polarity. Internal regulators provide
±5V
to the LTC1416/LTC1419. An LT1121-5 regulator
(U2) provides 5V for analog and digital circuitry; – 5V is
provided for the A/D and buffer by the MC79L05 regulator
(U1).
The Analog Input
The LTC1416/LTC1419 have a unique feature not found on
previous ADCs: differential inputs with good common
mode rejection from DC to over 10MHz. Although this
feature is extremely valuable for rejecting noise and mea-
suring differential signals, the board can also be used to
evaluate the LTC1416/LTC1419 in single-ended mode
(with the “–” input grounded). This board allows evalua-
tion in either mode.
Differential (bipolar) analog signals are applied to the
LTC1416/LTC1419 demo board using BNC connectors J4
(noninverting + input) and J5 (inverting – input). The
analog signal input range is
±2.5V.
4
U
The LTC1416/LTC1419 A
IN+
(noninverting) and A
IN–
(inverting) inputs have a common mode range of V
SS
to
V
DD
. The full-scale differential between the signals applied
to A
IN+
and A
IN–
is
±2.5V.
For example, when a 1.5V signal
is applied to the A
IN–
input, the negative-to-positive full-
scale input range of A
IN+
is –1V to 4V, corresponding to
an output code of 1000 0000 0000 to 0111 1111 1111.
The demo board is delivered with jumpers JP2 and JP4
closed. This configures the board for a
±2.5V
input signal
centered around ground and applied to J4 ( A
IN+
).
The board includes a recommended lowpass filter (R15
and R16, and C11) across the differential inputs. With the
component values shown, the cutoff frequency (f
S
) is:
1
= 1.56MHz
2π(102Ω)(1000pF)
These values can be altered to meet other circuit and input
signal requirements. For lower bandwidth input signals,
increase the value of C11. For undersampling applications
that take advantage of the input circuitry’s wide band-
width, decrease the capacitance of C11.
The best way to observe the performance of the LTC1416/
LTC1419 is to drive it directly from a low impedance signal
source. However, since some applications involve high
DEMO MANUAL DC200
HIGH SPEED ADC
OPERATIO
output impedance sources, the board also has provisions
for an onboard LT1363 high speed operational amplifier.
The LT1363, operating as a noninveting buffer, provides
the LTC1416/LTC1419 with a fast settling, low impedance
signal that allows the input voltage to settle fully between
conversions. The buffer is recommended if the source
impedance of the input signal is greater than 930Ω. The
LT1363 demonstrates how to properly drive the LTC1416/
LTC1419. When using the LT1363, open JP2 and close
JP4 and JP3.
Optimum performance is achieved using a signal source
that has low output impedance, is low noise and has low
distortion. Signal generators, such as the B & K Type 1051
Sine Generator, give excellent results. Further, this
generator can be configured to operate referenced to a
master clock signal, as shown in Figure 1.
Applying the Conversion Start Signal
A conversion is initiated by a falling edge on the CONVST
input (BNC J7). The CONVST input uses TTL or CMOS
levels. As shown in Figure 2, CONVST should remain low
until the conversion is completed or returned high within
420ns of the negative going edge, as shown in Figure 3.
During a conversion, transitions on the CONVST input can
cause errors in the D
OUT
output.
Reading the Output Data
The ADC data outputs are buffered by the two 74HC574
latches and are available on connector J6. The latches
drive the LEDs and connector J6. In a practical circuit,
latches are not required unless the ADC is tied to a noisy
data bus. (Refer to the LTC1416 or LTC1419 data sheet for
details on different digital interface modes.)
The output data format of the LTC1416/LTC1419 is two’s
complement. The data can be converted to offset binary by
using D13 instead of D13. Offset binary is used when an
FFT is to be performed on the sampled data. A Data Ready
line (J6, Pin 16) is provided to latch the D
OUT
word. D
OUT
is valid on the rising edge of Data Ready. Two ground lines
are provided on the connector and should be connected to
the receiving system.
U
The LTC1416/LTC1419 D
OUT
word can be acquired with a
logic analyzer. Conversion data can be stored on a disk and
easily transferred to a PC by using a logic analyzer that has
a PC compatible floppy drive (such as an HP1663A). Once
the data is transfered to a PC, use programs such as
MathCAD or Excel to calculate FFTs. Use the FFTs to obtain
LTC1416/LTC1419 AC specifications, such as signal-to-
noise ratio and total harmonic distortion.
REFERENCE
FREQUENCY
IN
BRUEL & KJAER
TYPE 1051 SINE
GENERATOR
V
IN
J4
LTC1416/
LTC1419
14-BIT A/D
DEMO BOARD
HEWLETT PACKARD
HP3326A
REFERENCE
GENERATOR
FREQUENCY
OUT
CLOCK
J7
J6
1-14
D
OUT
HEWLETT PACKARD
HP1663A
LOGIC
ANALYZER
CONVST
CLK
DC200 F01
Figure 1. Typical Setup for LTC1419 Demo Board
CONVST
BUSY
DATA READY
DC200 F02
Figure 2. Timing Diagram
<420ns
>40ns
CONVST
GOOD
BUSY
DATA READY
DC200 F03
Figure 3. Alternative Timing Diagram
5
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