APPLICATION NOTE
ATA6621, ATA6621N, ATA6622, ATA6622C, ATA6624,
ATA6624C, ATA6626, ATA6626C Development Board
ATA6621/22/24/26
Introduction
The development board for the Atmel
®
ATA6621/22/24/26 (ATA6621-EK, ATA6622-EK,
ATA6624-EK, ATA6626-EK) is designed to give designers a quick start with the ICs and for
prototyping and testing of new LIN designs.
The Atmel ATA6621, Atmel ATA6622, Atmel ATA6624 and Atmel ATA6626 are system
basis chips (SBCs) with fully integrated LIN transceiver, window watchdog with adjustable
trigger times and low-drop voltage regulator providing 5V/85mA (3.3V/85mA for the Atmel
ATA6622). The output current of the regulator can be boosted by using an external NPN
transistor.
The Atmel ATA6622 and the Atmel ATA6624 are totally pin- and function-compatible, the
only difference between these circuits is the regulator’s output voltage.
The ATA6626 has the same functionality as the ATA6624 without TXD time-out timer. The
ATA6626 is able to switch the LIN pin without any time limitation to dominant level via the
TXD input and is therefore particularly suited for low data rates.
The Atmel ATA6621 differs in a few more ways — an initial overview of these differences
starts with the different pins listed in
Table 1.
Table 1.
Overview of Pin Differences
Atmel ATA6621
PTRIG
Not connected
Not connected
Not connected
GND
TEMP
ATA6622/24/26
GND
GND
GND
INH
KL_15
GND
Pin No.
2
6
8
10
16
17
4970C-AUTO-06/15
Figure 1.
ATA6621/22/24/26 Development Board
Another difference is unequal watchdog timing (see
Section 1.3 on page 4).
The combination of the features included in the Atmel
®
ATA6621/22/24/26 makes it possible to develop simple, but powerful
and cheap, slave nodes in LIN-bus systems.
The ICs are designed to handle the low-speed data communication in vehicles, for example, in convenience electronics.
Improved slope control at the LIN driver ensures secure data communication up to 20Kbaud.
Sleep Mode and Silent Mode guarantee a very low current consumption.
This document has been developed to give the user an easy start with the development board of the Atmel
ATA6621/22/24/26. For more detailed information about the use of these devices themselves, refer to the corresponding
datasheets.
Development Board Features
The development board for the Atmel ATA6621/22/24/26 supports the following features:
●
All necessary components to put the Atmel ATA6621/22/24/26 in operation are included
●
●
●
●
●
Placeholders for some optional components for extended functions included
All pins easily accessible
Easily adaptable watchdog times by replacing a resistor
Possibility to place an external NPN transistor for boosting up the output current of the voltage regulator (jumper J1)
Possibility of selecting between master or slave operation (mounting D3 and R4)
2
ATA6621/22/24/26 [APPLICATION NOTE]
4970C–AUTO–06/15
Quick Start
The development board for the Atmel ATA6621/22/24/26 is shipped with all necessary components and a default jumper
setting to start with the development of a LIN slave node immediately.
After connecting an external 12V DC power supply between the terminals VB and GND, the circuit is in the Pre-normal mode
(Fail-safe mode) and a 5V (3.3V) DC voltage provided by the internal voltage regulator can be measured between VCC and
GND. (The Pre-normal mode is called Fail-safe mode in the datasheets of the devices Atmel ATA6622/24/26). Furthermore,
the following voltages or states can be measured at the pins WD_OSC, TEMP, INH, RXD and LIN:
Table 2.
Atmel ATA6621
Mode
Pre-normal mode
Normal mode
Table 3.
VCC
5V
5V
WD_OSC
2.5V
2.5V
TEMP
~2V
~2V
INH
-
-
RXD
5V
5V
LIN
Recessive
TXD dependent
Transceiver
Off
On
Atmel ATA6622
Mode
VCC
3.3V
3.3V
WD_OSC
1.23V
1.23V
TEMP
-
-
INH
On
On
RXD
3.3V
3.3V
LIN
Recessive
TXD dependent
Transceiver
Off
On
Fail-safe mode
Normal mode
Table 4.
Atmel ATA6624/26
Mode
VCC
5V
5V
WD_OSC
1.23V
1.23V
TEMP
-
-
INH
On
On
RXD
5V
5V
LIN
Recessive
TXD dependent
Transceiver
Off
On
Fail-safe mode
Normal mode
As the window watchdog of the Atmel
®
ATA6621/22/24/26 is already active in the Pre-normal mode (Fail-safe mode), a
periodic reset signal will be generated at the pin NRES as long as no trigger signal can be received at the watchdog trigger
input. Normally the connected microcontroller will be monitored by the watchdog, so it has to generate the required trigger
signal as described in
Section 1.3 on page 4
and in more detail in the datasheet of the corresponding device. For the quick
start it is sufficient to generate a square-wave signal with V
PP
= VCC and f = 75Hz at pin NTRIG or PTRIG for the Atmel
ATA6621 or with f = 50Hz at pin NTRIG for the Atmel ATA6622/24/26 (this is recommended only for testing purposes). In
order to check that the watchdog is triggered in the expected way, the reset pin NRES can be monitored until a continuous
high level is available.
Please note that the communication is still inactive in Pre-normal mode (Fail-safe mode).
In order to communicate via the LIN bus interface you have to switch to normal mode by applying the VCC voltage (5V or
3.3V, as appropriate) at pin EN.
ATA6621/22/24/26 [APPLICATION NOTE]
4970C–AUTO–06/15
3
1.
Hardware Description
In the following sections only the normal operating conditions will be described. For further information concerning one of the
mentioned features, refer to the corresponding datasheet.
1.1
Power Supply (VB and GND)
In order to get the development board running, an external 5.7V to 18V DC power supply is required between the terminals
VB and GND. The input circuit is protected against inverse-polarity with the protection diode D1, so that there is normally a
difference between the VB and VS level of approximately 0.7V.
1.2
Voltage Regulator (PVCC and VCC)
The internal 5V/3.3V voltage regulator is capable of driving loads up to 85mA so the SBCs are able to supply a
microcontroller, sensors and/or other ICs. The voltage regulator is protected against overloads by means of current limitation
and overtemperature shutdown. To boost the maximum load current, an external NPN transistor may be used, with its base
being connected to the VCC pin and its emitter connected to PVCC. If this is done, the regulated output voltage of 5V or 3.3V
is available at pin PVCC. For this reason, the pin PVCC and not the pin VCC is led to the connector available off the board.
But in normal operation, the pins PVCC and VCC have to be connected directly. This is done by setting jumper J1.
1.3
The Window Watchdog (PTRIG, NTRIG and NRES)
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG input (negative edge) within a defined time
window. The Atmel ATA6621 has an additional PTRIG input, so it is also possible to trigger the watchdog with a positive
edge. If no correct trigger signal is received, a reset signal will be generated at the NRES output. During Silent or Sleep
Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at the NRES pin disappears and is
defined as lead time t
d
.
The timing basis of the watchdog is provided by the internal oscillator, whose time period t
OSC
is adjustable via the external
resistor R3 at the pin WD_OSC. For the Atmel ATA6621, the voltage at this pin is 2.5V, for the Atmel ATA6622/24/26 it is
1.23V (see
Table 2 on page 3
through
Table 4 on page 3).
Due to these different voltages at the devices, the resulting timings
are also different. There is a resistor R3 with a value of 51k mounted on the development board, which results in the
following timing sequence for the Atmel ATA6621:
Figure 1-1. Timing Sequence with R3 = 51k at the Atmel ATA6621
V
CC
= 5V
Undervoltage Reset
NRES
t
reset
= 10ms
Watchdog Reset
t
nres
= 1.9ms
t
d
= 49ms
t
1
= 10ms
t
wd
t
2
= 10.5ms
t
1
t
2
NTRIG
PTRIG
t
trigg
> 3μs
4
ATA6621/22/24/26 [APPLICATION NOTE]
4970C–AUTO–06/15
For the Atmel
®
ATA6622/24/26 the resistor R3 at pin WD_OSC with the same value of 51k results in the different timing
sequence shown in
Figure 1-2:
Figure 1-2. Timing Sequence with R3 = 51k at the Atmel ATA6622/24/26
V
CC
= 3.3V/5V
Undervoltage Reset
NRES
t
reset
= 4ms
Watchdog Reset
t
nres
= 4ms
t
d
= 150ms
t
1
= 20ms
t
wd
t
2
= 21ms
t
1
t
2
NTRIG
t
trigg
> 200ns
If you want to change the watchdog times mentioned above it is only necessary to change the value of the external resistor
R3 (refer to the corresponding datasheet).
1.4
1.4.1
LIN Interface (LIN, TXD and RXD)
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor in compliance
with the LIN specification 2.0 is implemented. LIN receiver thresholds are compatible with the LIN protocol specification.
At the LIN pin there is a 220-pF capacitor to ground on the board. Additionally, when using the development board for a LIN
master application, there is the opportunity to mount the two necessary extra components diode D2 (LL4148) in series with
resistor R1 (1k) on the board at their designated placeholders.
1.4.2
Input Pin (TXD)
In Normal Mode this pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground
in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state,
pulled up by the internal resistor. If TXD is low, the LIN output transistor is turned on and the bus is in the dominant state.
An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer
than t
DOM
> 20ms, the LIN bus driver is switched to the recessive state. This time-out function is disabled in the Atmel
ATA6626.
1.4.3
Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD,
LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typ. 5k to VCC.
The output is short-circuit protected.
ATA6621/22/24/26 [APPLICATION NOTE]
4970C–AUTO–06/15
5
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