quiescent current surge stopper in an application which
can be configured for 12V, 1A or 24V/28V, 0.5A operation.
The output voltage is clamped by the LTC4380, permitting
the load to operate uninterrupted during transients of up to
250V and load dump surges such as ISO-16750-2 Test A.
The output current is limited to 1.25A. In the presence of
a sustained input overvoltage or output overcurrent fault
the LTC4380 shuts off to prevent damage to the N-channel
MOSFET pass element.
The output clamp voltage is selected by jumper JP1 to a
value of either 27V or 45V, to suit 12V or 24V/28V sys-
tems. DC2178A-A features the LTC4380-1 which latches
off after a fault, and DC2178A-B features the LTC4380-2
which automatically retries after a cool down delay.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2178A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
operating characteristics
System Voltage
Clamp Select
DC Operating (Full Load)*
DC Survival
Surge Ride-Through**
1ms Transient
Onset of Current Limit
Short Circuit Current
Maximum Load (V
IN
> 9V)
12V
27V
9V to 20V
80V
ISO-16750-2 Test A
250V
1.25A
1.55A
1A
24V/28V
45V
9V to 37.5V
80V
ISO-16750-2 Test A
250V
1.25A
1.55A
0.5A
* Initial production boards are marked with more conservative limits of 19V and 35V. Functionality extends to 4.2V at 25°C. All boards are tested to the
limits shown in the table above.
** Formerly ISO-7637-2 Test Pulse 5A
dc2178af
1
DEMO MANUAL DC2178A
operating characteristics
DANGER! High voltage testing shall be performed by
qualified personnel only. As a safety precaution at least
two people shall be present during high voltage testing.
Board Layout
DC2178A is a 2 layer board. There are planes for input,
output and ground; these are replicated on both layers.
There are exposed conductors on the bottom of the board,
and any banana plugs present will protrude through the
bottom of the board. The underlying surface should be
non-conductive and clear of any wire, solder and other
conductive debris.
The input plane is designed to have at least 79 mil (2mm)
clearance to adjacent conductors, to support 80VDC
standoff and transients to 250V. Spikes and surges are
withstood by R1, RDRN, CSNUB and Q1. These components
are chosen for wide pad spacing, pulse power capability
and voltage standoff, but ultimately limit the maximum
transient input voltage to approximately 250V. The time
spent above 80V is limited by the pulse power capability
of Q1 and R1.
Operation
DC2178A is designed for 12V operation with a load of up
to 1A, and 24V or 28V operation with a load of up to 0.5A.
JP1 selects an output clamping voltage of either 27V or
45V. For 24V and 28V supplies use a clamping voltage
of 45V; 12V supplies may use either 27V or 45V. If the
load tolerates the higher voltage, 45V clamping is better
than 27V in 12V applications because it reduces the drop
across the MOSFET (Q1) and therefore the safe operating
area stress, giving longer ride-through time during an
overvoltage condition.
Q1 is selected to ride through load dump events (such as
ISO 16750-2 Test A) with full load in 12V (1A) and 24V/28V
(0.5A) systems. Ride through is also permissible at 1A
for a 250V input transient of up to 1ms.
Up to 80VDC can be applied to the input. The circuit will trip
off after a delay of approximately 350ms for 1A load and
a 27V clamp, or 800ms for a 0.5A load and a 45V clamp.
The TMR pin charging current is a function of the power
dissipated in Q1 so that the exact delay time is a function
of the input voltage, output voltage and load current.
The LTC4380 features current limiting, which is set with
RSNS (40mΩ) to a value of 1.25A. Current limit does not
change with operating voltage or clamping voltage selec-
tion. If the output is shorted so that the output voltage falls
to 2V or less, current limit increases to 1.55A. In current
limit, the LTC4380 trips off after a delay that varies as a
function of the dissipation in Q1.
While the LTC4380 is designed to withstand reverse inputs
of up to −60V, DC2178A does not tolerate negative-going
events because Q1’s body diode will pass the negative
voltage straight through to the output and load. Nega-
tive inputs are easily blocked by the addition of a series
input diode, or by adding a second MOSFET as shown in
Figures 5 and 7 of the LTC4380 data sheet.
The LTC4380-1/LTC4380-2 V
CC
pin is rated at 80V maxi-
mum. Power is applied from the input to the V
CC
pin through
a 20kΩ resistor (R1), filtered by a 2.2μF capacitor (C1A),
and clamped by D1 to 68V. This arrangement offers two key
benefits. First, C1 filters the V
CC
pin to maintain operation
during brief input dropouts and to filter overvoltage spikes.
Second, during load dump in 24V/28V applications V
CC
is
clamped by D1 to keep the V
CC
pin safely below 80V. D1
is unnecessary in 12V applications because the filtering
action provided by C1 is sufficient to keep the V
CC
pin
below 80V, even in load dump.
12V Cold Crank Operation
An FDB33N25 was chosen for MOSFET Q1 to satisfy two
requirements: ability to block load dump (≈200V) in 28V
systems; and wide safe operating area for uninterrupted
operation during load dump events. The penalty for these
features is a high threshold voltage of 5V maximum at
I
D
= 250μA and 25°C, with no guarantees at temperature
extremes. R1 was chosen to limit the peak current in D1
to a safe level with 250V peak input voltage, but it also
reduces the V
CC
voltage below the input under normal
conditions. Q1 and R1 impact cold crank operation in
12V systems.
The LTC4380 is designed to deliver 10V of gate drive with
V
CC
> 8V, and 5V with V
CC
between 4V and 8V, guaranteed
over temperature. Thus, the FDB33N25 is incompatible
with operation in the 4V to 8V range, although typical
DC2178A assemblies can deliver 500mA load current
dc2178af
2
DEMO MANUAL DC2178A
operating characteristics
with an input voltage of 4.2V. For full performance in
12V cold crank applications, a logic-level rated MOSFET
is necessary for Q1.
Optional Components
Pads are provided for optional V
CC
bypassing at C1B (C1A
is stuffed with 2.2μF), and for optional timer capacitance
at CTMR2 (CTMR1 is stuffed with 10μF). C1B and CTMR2
are found on the bottom of the board.
An optional GATE pin clamp (D6) is also located on the
bottom of the board. This clamp is necessary in applications
where a large value gate capacitor (C2 ≥ 100nF) is used.
A 15V Zener is recommended for D6, to safely discharge
C2 during a hard short circuit.
Extra Holes
Five through-hole pads are included for the purpose of
attaching an off-board power stage comprising a MOS-
FET, gate suppression resistor, sense resistor and output
reservoir capacitor in high current applications, where the
components and current levels are not compatible with
the layout of DC2178A. The pads are labeled on the bot-
tom of the board and noted on the schematic as INPUT,
OUT, GATE, SNS and GND. Remove Q1 and RSNS. Make
short, direct connections between the through-hole pads
and the external components, and use SNS and OUT to
make Kelvin connections to the sense resistor. Depending
on the setup and MOSFET used, a snubber may be needed
between the MOSFET drain and the ground side of the
output reservoir capacitor, or between the MOSFET drain
and source terminals to suppress parasitic oscillations.
Small Turrets
No connection to any of the small turrets is necessary
to make the board operate—the LTC4380 defaults to the
ON state.
ON is pulled high internally. If this turret is left open, the
board will turn on when power is applied. Short this turret
to ground to turn off the LTC4380, or pulse low for at least
100μs to restart the LTC4380-1 (DC2178A-A) after a fault.
FLT
pulls low when the LTC4380 faults off from an overcur-
rent or overvoltage condition. It is reset by pulling the ON
pin low for at least 100μs in the LTC4380-1 (DC2178A-A),
or after a cool down interval in the LTC4380-2 (DC2178A-B).
FLT
can sink up to 3mA.
Jumpers
Jumper JP1 sets the state of the SEL pin to select between
a 27V output clamp (SEL grounded) or a 45V output clamp
(SEL connected to OUT). The corresponding clamp volt-
age at the GATE pin is about 5V higher than these values.
Jumper JP2 disables the output LED (DLED) to facilitate
measurement of the LTC4380’s operating current.
Basic Test Setup
DANGER! High voltage testing shall be performed by
qualified personnel only. As a safety precaution at least
two people shall be present during high voltage testing.
Set the jumper, JP1, for 12V or 24V/48V operation, con-
nect a power supply to the input, and connect a load to
the output as shown in Figure 1. The circuit will turn on
automatically when power is applied, and the presence of
output power is indicated by the output LED.
To perform surge testing, add a diode (such as a 1N4004)
in series with the power supply. Couple the surge generator
through a second diode to the input to test the clamping
action of DC2178A. The diodes protect the power supply
and surge generator against backfeeding.
To measure the operating current, disable the output LED
using JP2, and disconnect the load.
dc2178af
3
DEMO MANUAL DC2178A
operating characteristics
JP1
INPUT
SUPPLY
OUTPUT
LOAD
Figure 1. Basic Setup. JP1 Is Set to Match Input Supply, 27V Clamp
for 12V Supplies and 45V Clamp for 12V or 24V/28V Supplies
4
dc2178af
E1
INPUT
Q1
FDB33N25
RSNS
0.040
OUTPUT
E3
INPUT
2
1
3
INPUT
OUTPUT
+
J3
E4
CL
22uF
50V
J1
1
E2
R3
10
RSNUB
100
1210
DLED
GREEN
2
GND
GATE
D6
DDZ9702S
1
2
15V
OPT
R2
33
SNS
JP2
HD2X2-079
OUT
RDRN
240k
1206
R1
20k
1206
CSNUB
10nF
500V
1206
RLED2
3.6k
1206
GND
J4
schematic Diagram
J2
VCC
1
1
3
ON
OFF
LED
2
4
RLED1
3.6k
1206
2
D1
CMHZ5266B
68V
C2
47nF
100V
C1B
OPT
1210
C1A
2.2uF
100V
1210
2
3
4
1
VCC
SNS
DRN
GATE
OUT
EP
11
6
SEL
DFN10DD-3X3
U1
ON
GND
FLT
*
8
7
TMR
10
9
5
CLAMP
3
4
1
2
JP1
HD2X2-079
45V
27V
CTMR2
OPT
1206
GND
CTMR1
10uF
10V
1206
E5
E6
E7
E8
E9
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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