DEMO MANUAL
DC1814A
LTC4274A
Single LTPoE++ PSE Controller
Description
Demonstration circuit 1814A features the
LTC
®
4274A,
single port power sourcing equipment (PSE) controller,
capable of delivering up to 90W of LTPoE++
®
power to a
compatible LTPoE++ powered device (PD). A proprietary
detection/classification scheme allows mutual identifica-
tion between an LTPoE++ PSE and LTPoE++ PD while
remaining compatible and interoperable with existing
Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4274A
feature set is a superset of the popular LTC4274. These
PSE controllers utilize low R
ON
external MOSFETs and
0.25Ω sense resistors which are especially important at
the LTPoE++ current levels to maintain the lowest possible
heat dissipation.
The LTC4274A is available in multiple power grades,
allowing delivered PD power of 13W, 25.5W, 38.7W,
52.7W, 70W and 90W. The DC1814A has four variations
DC1814A-A, DC1814A-B, DC1814A-C, and DC1814A-D
which accommodate the LTPoE++ power levels (Table 1).
Table 1. DC1814A Power Levels
DEMO BOARD
DC1814A-A
DC1814A-B
DC1814A-C
DC1814A-D
PSE CONTROLLER
LTC4274A-1
LTC4274A-2
LTC4274A-3
LTC4274A-4
MAXIMUM DELIVERED PD POWER
38.7W
52.7W
70W
90W
POWER SUPPLY*
72W
72W
120W
140W
The LTC4274A is configured in the DC1814A as an AUTO
pin high, MID pin high, autonomous midspan power injec-
tor; input data from an existing network system is sent out,
along with power, to a PD. The LTC4274A autonomously
detects a PD, turns power on to the port, and disconnects
port power without the need for a microcontroller. A single
55V supply is required to power the DC1814A. A simple
LDO regulator circuit on the board powers the digital sup-
ply of the LTC4274A. A
SHDN
pushbutton shuts down the
port and disables detection. A
RESET
pushbutton resets
the LTC4274A to the AUTO pin high state.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1814A
L,
LT, LTC, LTM, LTPoE++, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
*Recommended DC1814A power supply minimum to avoid drooping in a worst-case scenario with I
LIM
current at the port. Set the voltage between
54.75V to 57V for LTPoE++ compliance.
dc1814afe
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DEMO MANUAL
DC1814A
Quick start proceDure
Demonstration circuit 1814A is easy to set up for evaluat-
ing the performance of the LTC4274A. Refer to Figure 1
for proper test equipment setup and follow the procedure
below.
1. Connect a 55V to 57V power supply across AGND (+)
and VEE (–). Size the power supply considering the
maximum power delivered to the PD.
2. Connect an 802.3 Type 1 or Type 2, or LTPoE++ compat-
ible PD to RJ45 connector J1 with an Ethernet cable.
3. Measure the port output voltage to the PD across
VPORT+ and VPORT– test points.
4. (Optional) Connect a PHY to RJ45 connector J2 with
an Ethernet cable for data tests.
Figure 1. DC1814A Setup
2
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DEMO MANUAL
DC1814A
BoarD Layout
Proper components placement and board layout with
respect to the LTC4274A is important to provide electrical
robustness and correct operation. The following mentioned
components, also shown in Figure 2, must be close to their
respective LTC4274A pins with no other components in
between on the connection path. Place a 0.1µF capacitor
(C1) directly across the LTC4274A VDD and DGND pins.
Place a 1µF 100V capacitor (C4) and a SMAJ58A TVS (D3)
,
directly across the LTC4274A AGND and VEE pins. Place
a 0.22µF 100V capacitor (C5) directly to the OUT pin and
,
an AGND plane.
The power path is from VEE to the sense resistor, to the
MOSFET, and out to the port. Select a trace width appro-
priate for the maximum current.
Kelvin sensing is necessary to provide accurate current
readings. The sense resistor used with the LTC4274A must
be 0.25Ω, 1% or better, and with a power rating that can
handle the maximum DC current passed through it. A
dedicated sense trace from the SENSE pin of the LTC4274A
must go directly to the sense resistor solder pad. Avoid
connecting to copper cutouts and other traces. The VEE
side of the sense resistor must also connect to the VEE
pins of the LTC4274A either through a direct trace (Figure
3A), or a VEE copper plane (Figure 3B), without any other
components in between on this connection.
VDD
C1
0.1µF
DGND
13
VDD
U1
LTC4274AIUHF
SENSE
AGND
GATE
31
18
19 22 25 26 27 39
30
D3
SMAJ58A
VEE
C4
0.1µF
100V
OUT
32
C5
0.22µF
100V
OUT
VEE
VEE
VEE
VEE
VEE
VEE
RS1
0.25
10
15
16
17
DGND
DGND
DGND
DGND
Q1
CSRN2512FKR250
FDMC86102
DC1814A F02
Figure 2. LTC4274A Key Application Components for Board Placement
Figure 3. LTC4274IUHF VEE and SENSE Kelvin Connection to Sense Resistor
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DEMO MANUAL
DC1814A
suppLy VoLtages
Select a VEE supply with enough power to sustain the port
at maximum load. Table 1 shows the maximum delivered
PD power as well as a recommended VEE power supply
minimum to avoid drooping in a worst case scenario with
I
LIM
current.
The LTC4274A also requires a digital 3.3V supply. The
DC1814A uses a simple LDO regulator circuit to power the
3.3V digital supply from the VEE supply. The LTC4274A VDD
supply is allowed to be within 5V above or below AGND. On
the DC1814A, VDD is tied to AGND and DGND is a negative
voltage below AGND. D1, R5, Q2, and R11 generate the
negative voltage referenced to AGND (Figure 4). These
components are sized to handle the power required to
supply the LTC4274A and LEDs on the DC1814A. Contact
Linear Technology Applications for 3.3V options.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components
are required at the main supply, at the LTC4274A supply
pins and at the port. Refer to Figure 5.
R10
1
Bulk transient voltage suppression devices and bulk
capacitance are required across the main PoE supply
and should be sized to accommodate system level surge
requirements. Across the LTC4274A AGND pin and VEE
pin are an SMAJ58A, 58V TVS and a 1μF 100V bypass
,
capacitor. These components must be placed close to the
LTC4274A pins.
In a high surge environment, a 10Ω, 0805 resistor in series
from supply AGND to the LTC4274A AGND and VDD pin is
recommended. The bulk TVS and capacitance remain on
the supply side of this 10Ω resistor. The LTC4274A supply
pins local TVS and capacitance remain at the LTC4274A
side of this 10Ω resistor.
The port requires a pair of S1B clamp diodes: one from
OUT to supply AGND and one from supply VEE to OUT. The
diodes at the ports steer harmful surges into the supply
rails where they are absorbed by the surge suppressors
and the VEE bypass capacitance. The layout of these paths
must be low impedance.
13
C1
0.1µF
10
15
16
17
VDD
U1
LTC4274AIUHF
D1
3.8V
MMSZ4686T1
D23
5.6V
DGND
Q2
CMPTA92
R5
100k
AGND
18 19 22 25 26 27 39
R11
1k
1/4W
VEE
DC1814A F04
Figure 4. DC1814A LDO Circuit for the LTC4274A Digital Supply
VEE
VEE
VEE
VEE
VEE
VEE
DGND
DGND
DGND
DGND
4
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DEMO MANUAL
DC1814A
suppLy VoLtages
10Ω
0805
D1
3.9V
MMSZ4686T1
R10
1
13
C1
0.1µF
10
15
16
17
DGND
DGND
DGND
DGND
VDD
TVS
BULK
VEE
C
BULK
D23
5.6V
U1
LTC4274AIUHF
SENSE
AGND
GATE
31
R5
100k
18
19 22 25 26 27 39
30
R11
1k
1/4W
VEE
D3
SMAJ58A
C4
1µF
100V
OUT
32
C5
0.22µF
100V
VEE
VEE
VEE
VEE
VEE
VEE
Q2
CMPTA92
RS1
0.25
CSRN2512FKR250
Q1
FDMC86102
D4
S1B
OUT
D5
S1B
VEE
DC1814A F05
Figure 5. High Surge Environment Recommended LTC4274A Protection
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