DATA SHEET
SMP1330-085LF: Surface Mount Limiter Diode
Applications
Low loss, high power limiters
Receiver protectors
Anode
(Pin 1)
Anode
(Pin 3)
Features
Low thermal resistance: 91
°C/W
Typical threshold level: +9 dBm
Low capacitance: 0.55 pF
Low profile, ultra-miniature QFN (3-pin, 2 x 2 mm) package
(MSL1, 260
C
per JEDEC J-STD-020)
Skyworks
Green™ products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to
Skyworks
Definition of Green™,
document number
SQ04-0074.
Cathode
(Pin 2, Exposed Paddle)
Figure 1. SMP1330-085LF Block Diagram
Description
The SMP1330-085LF is a surface mountable, low capacitance
silicon PIN limiter diode designed as a shunt connected PIN diode
for high power limiter applications up to 6
GHz.
Maximum resistance at 10 mA is 2
Ω
and maximum capacitance
at 0 V is 0.55 pF. The combination of low junction capacitance,
low parasitic inductance, low thermal resistance, and nominal
2
μm
I-region width, makes the SMP1330-085LF useful in large
signal limiter applications. The threshold level is +9 dBm
at 1
GHz.
A block diagram of the SMP1330-085LF is shown in Figure 1. The
absolute maximum ratings of the SMP1330-085LF are provided in
Table 1. Electrical specifications are provided in Table 2.
Typical performance characteristics of the SMP1330-085LF are
provided in Table 3 and illustrated in Figure 4.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201326I • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 20, 2013
1
DATA SHEET • SMP1330-085LF SURFACE MOUNT LIMITER DIODE
Table 1. SMP1330-085LF Absolute Maximum Ratings
Parameter
Reverse voltage
Forward current @ 25
°C
CW power dissipation @ 25
°C
Peak pulse power dissipation @ 25
°C
(10% duty cycle)
Storage temperature
Junction temperature
Operating temperature
Electrostatic discharge:
Human Body Model (HBM), Class 1A
Note:
Symbol
V
R
I
F
P
D
Minimum
Maximum
50
200
0.75
7.5
Units
V
mA
W
W
C
C
C
T
STG
T
J
T
A
ESD
–65
+175
175
–40
+150
250
500
V
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION:
Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 2. SMP1330-085LF Electrical Specifications (Note 1)
(T
A
= +25
C
Unless Otherwise Noted)
Parameter
Breakdown voltage
Reverse current
Capacitance
V
B
I
R
C
T
Symbol
Test Condition
I
R
= 10
μA
V
R
= 24 V
f = 1 MHz:
V
R
= 0 V
V
R
= 6 V
Capacitance ratio
Series resistance
Carrier lifetime
I region width
CW thermal resistance
Peak thermal resistance
C
TR
R
S
T
L
W
θ
JC
θ
P
Junction-to-case
Single 1
μs
pulse width,
junction-to-case (10%
duty cycle)
C
T
@ 0 V/C
T
@ 6 V
f = 100 MHz, I
F
= 10 mA
I
F
= 10 mA
1.6
13
2
91
0.55
0.50
1.00
0.60
1.22
2.0
pF
pF
–
Ω
ns
μm
C/W
Min
30
Typical
Max
50
100
Units
V
nA
9
C/W
Note 1:
Performance is guaranteed only under the conditions listed in this Table.
Table 3. Typical 1 GHz Limiter Performance
Parameter
Connection
Insertion loss
IP3
1 dB compression
Attenuation @ +20 dBm
Attenuation @ +30 dBm
Parallel
0.1 dB
+30 dBm
+9 dBm
8.8 dB
14 dB
Input power = –10 dBm
Input power = < 0 dBm
SMP1330-085LF
Condition
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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November 20, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201326I
DATA SHEET • SMP1330-085LF SURFACE MOUNT LIMITER DIODE
Functional Description
The PIN limiter diode can be described as an incident power
controlled, RF variable resistor. When there is no large input
signal present, the impedance of the limiter diode is at its
maximum, which produces minimum insertion loss, typically
less than 0.1 dB. The presence of a large input signal
temporarily forces the impedance of the diode to a much lower
value, which produces an impedance mismatch that reflects the
majority of the input signal power back towards its source.
During the limiting process, a DC current is generated by the
PIN limiter diode. The current is not the result of rectification,
but is the result of charge carriers being forced into the I layer
by the forward alternations of the large input signal. A complete
path must be provided for this current or the diode is not
capable of limiting. Therefore, an RF choke or similar structure
must be provided to complete the path for DC current flow.
The DC block capacitors shown in Figure 2 are optional; they
protect the limiter diode from external DC voltage that may be
present in the source or load circuits.
A cross section of the suggested printed circuit board design is
shown in Figure 3. The via shown in this view is critical, both for
electrical performance and for thermal performance. It is
recommended that several vias should be placed under the
entire footprint of the exposed paddle (pin 2) to minimize both
electrical inductance to the system ground and thermal
resistance to the system heat sink.
For more information about the operation of limiter diodes, refer
to the Skyworks Application Note,
PIN Limiter Diodes in
Receiver Protectors,
document number 200480.
DC
Block
Input
Limiter
PIN
DC
Block
Output
RF
Choke
Figure 2. Single Stage Limiter Circuit
SMP1330-085LF
Thermal Via
S1630c
Figure 3. Cross-Sectional View of Suggested Printed Circuit Board
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201326I • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 20, 2013
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DATA SHEET • SMP1330-085LF SURFACE MOUNT LIMITER DIODE
Typical Performance Characteristics
(T
A
= 25
°C,
Unless Otherwise Noted)
+25
+20
Output Power (dBm)
+15
+10
+5
0
0
+10
+14
+18
+22
+26
+30
Input Power (dBm)
Figure 4. Output Power and Insertion Loss vs Input Power
(f = 2.0 GHz)
High Power Limiter Design Application
The SMP1330-085LF PIN limiter diode is designed for shunt
applications in receiver protection power limiter circuits.
Compared to other surface mount packages, the design of the
QFN package produces lower thermal resistance and also reduces
the effects of the parasitic inductance of the anode bond wires.
A cross-sectional view of the SMP1330-085LF PIN limiter diode is
shown in Figure 5. The cathode of the die is soldered directly to
the top of the exposed paddle. This paddle is composed of
copper, so its thermal resistance is very low.
The copper ground paddle minimizes the total thermal resistance
between the I layer, which is the location where most heat is
generated under normal operation, and the surface to which the
package is mounted. Minimal thermal resistance between the
I layer and the external environment minimizes junction
temperature.
The electrically equivalent circuit of the SMP1330-085LF PIN
limiter diode is shown in Figure 6. The inductances of pins 1 and
2, as well as the inductances of the bond wires are in series with
the input and output transmission lines of the external circuit
rather than the portion of the circuit that contains the shunt PIN
limiter diode.
Bond Wire
(2 Places)
Encapsulated
Epoxy
SMP1330-085LF
Die
Anode
(Pin 1)
Not to scale
Cathode
(Pin 2)
Anode
(Pin 3)
S1628c
Figure 5. Cross-Sectional View of the SMP1330-085LF
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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November 20, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201326I
DATA SHEET • SMP1330-085LF SURFACE MOUNT LIMITER DIODE
L
SERIES
Pin 1
L
SERIES
Pin 3
C
PKG
SMP1330-085LF
Die
C
PKG
L
PADDLE
Pin 2
S1629c
Figure 6. SMP1330-085LF Electrically Equivalent Circuit
2X 0.60
Part Outline
2X 0.55
Exposed
Soldering
Area Typ.
2X 0.27
Pin 3
Pin 2
R0.20
2X 0.25
Figure 7. SMP1330-085LF PCB Layout Footprint
2X 0.85
Pin 1
S2923
Package Dimensions
The PCB layout footprint for the SMP1330-085LF is shown in
Figure 7. Typical part markings are shown in Figure 8. Package
dimensions for the 3-pin QFN are provided in Figure 9, and
Figure 10 provides the tape and reel dimensions.
The SMP1330-085LF is rated to Moisture Sensitivity Level 1
(MSL1) at 260
C.
It can be used for lead or lead-free soldering.
For additional information, refer to the Skyworks Application Note,
Solder Reflow Information,
document number 200164.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format.
Package and Handling Information
Instructions on the shipping container label regarding exposure to
moisture after the container seal is broken must be followed.
Otherwise, problems related to moisture absorption may occur
when the part is subjected to high temperature during solder
assembly.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201326I • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 20, 2013
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