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ATSAMD51J20A-UUT

Description
120MHZ 1024KB FLASH 64 WLCSP PKG
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size13MB,2126 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Download user manual Parametric View All

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ATSAMD51J20A-UUT Overview

120MHZ 1024KB FLASH 64 WLCSP PKG

ATSAMD51J20A-UUT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionWLCSP-64
Reach Compliance Codecompliant
Samacsys DescriptionARM Microcontrollers - MCU 120MHZ 1024KB FLASH 64 WLCSP PKG IN 85C
Has ADCYES
Address bus width
bit size32
maximum clock frequency48 MHz
DAC channelYES
DMA channelYES
External data bus width
JESD-30 codeR-PBGA-B64
JESD-609 codee3
length3.593 mm
Number of I/O lines51
Number of terminals64
On-chip program ROM width8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
ROM programmabilityFLASH
Filter levelISO/TS-16949
Maximum seat height0.533 mm
speed120 MHz
Maximum supply voltage3.63 V
Minimum supply voltage1.71 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formBALL
Terminal pitch0.4 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.513 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
SAMD5x/E5x Family Data
Sheet
32-bit ARM® Cortex®-M4F MCUs with 1 Msps 12-bit ADC,
QSPI, USB, Ethernet, and PTC
Features
Operating Conditions:
-40°C to +85°C, DC to 120 MHz
403 CoreMark
®
at 120 MHz
4 KB combined instruction cache and data cache
8-zones Memory Protection Unit (MPU)
Thumb
®
-2 instruction set
Embedded Trace Module (ETM) with instruction trace stream
Core Sight Embedded Trace Buffer (ETB)
Trace Port Interface Unit (TPIU)
Floating Point Unit (FPU)
Core: 120 MHz ARM
®
Cortex
®
-M4
Memories
1 MB/512 KB/256 KB in-system self-programmable Flash with:
– Error Correction Code (ECC)
– Dual bank with Read-While-Write (RWW) support
– EEPROM hardware emulation
256/192/128 KB SRAM Main Memory
– 128/96/64 KB of Error Correction Code (ECC) RAM option
Up to 4 KB of Tightly Coupled Memory (TCM)
Up to 8 KB additional SRAM
– Can be retained in backup mode
Eight 32-bit backup registers
System
Power-on Reset (POR) and Brown-out detection (BOD)
Internal and external clock options
External Interrupt Controller (EIC)
16 external interrupts
One non-maskable interrupt
Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
Power Supply
Idle, Standby, Hibernate, Backup, and Off sleep modes
©
2018 Microchip Technology Inc.
Datasheet
DS60001507B-page 1
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