IDT71T75602S133BGI datasheet, PDF

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IDT71T75602S133BGI: Description512K X 36 ZBT SRAM, 4.2 ns, PBGA119; Categorystorage; File Size234KB，26 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT71T75602S133BGI Overview

512K X 36 ZBT SRAM, 4.2 ns, PBGA119

IDT71T75602S133BGI Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	119
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	2.62 V
Minimum supply/operating voltage	2.38 V
Rated supply voltage	2.5 V
maximum access time	4.2 ns
Processing package description	14 X 22 MM, MS-028-AA, BGA-119
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	GRID ARRAY
surface mount	Yes
Terminal form	BALL
Terminal spacing	1.27 mm
terminal coating	TIN LEAD
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	36
organize	512K X 36
storage density	1.89E7 deg
operating mode	SYNCHRONOUS
Number of digits	524288 words
Number of digits	512K
Memory IC type	ZBT SRAM
serial parallel	PARALLEL

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512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

◆

IDT71T75602

IDT71T75802

Features

◆

512K x 36, 1M x 18 memory configurations

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

◆

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

Green parts available, see Ordering Information

Functional Block Diagram - 512K x 36

LBO

512Kx36 BIT

MEMORY ARRAY

Address

Address A [0:18]

CE1

CE2

CEN

ADV/LD

Control

Input Register

Clk

Control Logic

Mux

Sel

Clock

Output Register

Gate

Clk

TMS

TDI

TCK

TRST

(optional)

JTAG

TDO

Data I/O [0:31],

I/O P[1:4]

5313 drw 01

OCTOBER 2017

DSC-5313/11

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