LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash;
up to 12 kB SRAM; USB device; USART; EEPROM
Rev. 3 — 20 September 2012
Product data sheet
1. General description
The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1315/16/17/45/46/47 operate at CPU frequencies of up to 72 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller
available on the LPC1345/46/47, this series brings unparalleled design flexibility and
seamless integration to today’s demanding connectivity solutions.
The peripheral complement of the LPC1315/16/17/45/46/47 includes up to 64 kB of flash
memory, 8 kB or 10 kB of SRAM data memory, one Fast-mode Plus I
2
C-bus interface, one
RS-485/EIA-485 USART with support for synchronous mode and smart card interface,
two SSP interfaces, four general purpose counter/timers, an 8-channel, 12-bit ADC, and
up to 51 general purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M3 r2p1 processor, running at frequencies of up to 72 MHz.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 64 kB on-chip flash program memory with a 256 byte page erase function.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash updates via USB supported.
Up to 4 kB on-chip EEPROM data memory with on-chip API support.
Up to 12 kB SRAM data memory.
16 kB boot ROM with API support for USB API, power control, EEPROM, and flash
IAP/ISP.
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
Debug options:
Standard JTAG test interface for BSDL.
Serial Wire Debug.
Support for ETM ARM Cortex-M3 debug time stamping.
Digital peripherals:
Up to 51 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins
support programmable glitch filter.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin (P0_7).
High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a internal low-power
WatchDog Oscillator (WDO).
Repetitive Interrupt Timer (RI Timer).
Analog peripherals:
12-bit ADC with eight input channels and sampling rates of up to 500 kSamples/s.
Serial interfaces:
USB 2.0 full-speed device controller (LPC1345/46/47) with on-chip ROM-based
USB driver library.
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator)
with failure detector.
12 MHz high-frequency Internal RC oscillator (IRC) trimmed to 1 % accuracy over
the entire voltage and temperature range. The IRC can optionally be used as a
system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB (LPC1345/46/47).
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
2 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power-On Reset (POR).
Brownout detect with up to four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (2.0 V to 3.6 V).
Temperature range
40 C
to +85
C.
Available as LQFP64, LQFP48, and HVQFN33 package.
3. Applications
Consumer peripherals
Medical
Industrial control
Handheld scanners
USB audio devices
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC1345FHN33
LPC1345FBD48
LPC1346FHN33
LPC1346FBD48
LPC1347FHN33
LPC1347FBD48
LPC1347FBD64
LPC1315FHN33
LPC1315FBD48
LPC1316FHN33
LPC1316FBD48
LPC1317FHN33
LPC1317FBD48
LPC1317FBD64
HVQFN33
LQFP48
HVQFN33
LQFP48
HVQFN33
LQFP48
LQFP64
HVQFN33
LQFP48
HVQFN33
LQFP48
HVQFN33
LQFP48
LQFP64
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
SOT313-2
SOT314-2
Type number
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; n/a
body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
SOT313-2
SOT314-2
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
3 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Flash
[kB]
SRAM [kB]
SRAM0 USB
SRAM
LPC1345FHN33
LPC1345FBD48
LPC1346FHN33
LPC1346FBD48
LPC1347FHN33
LPC1347FBD48
LPC1347FBD64
LPC1315FHN33
LPC1315FBD48
LPC1316FHN33
LPC1316FBD48
LPC1317FHN33
LPC1317FBD48
LPC1317FBD64
32
32
48
48
64
64
64
32
32
48
48
64
64
64
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
-
-
-
-
-
-
-
SRAM1
-
-
-
-
2
2
2
-
-
-
-
2
2
2
2
2
4
4
4
4
4
2
2
4
4
4
4
4
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
8
8
8
8
8
8
8
8
8
8
8
8
8
26
40
26
40
26
40
51
28
40
28
40
28
40
51
EEPROM USB
SSP I2C/ FM+ ADC
[kB]
device
channels
GPIO
pins
Type number
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
4 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
RESET
LPC1315/16/17
LPC1345/46/47
TEST/DEBUG
INTERFACE
SYSTEM OSCILLATOR
IRC, WDO
BOD
POR
PLL0
USB PLL
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
CLKOUT
ARM
CORTEX-M3
EEPROM
2/4 kB
system bus
SRAM
8/10/12 kB
slave
GPIO ports 0/1
HIGH-SPEED
GPIO
slave
AHB-LITE BUS
ROM
16 kB
FLASH
32/48/64 kB
slave
slave
master
USB DEVICE
slave CONTROLLER
(LPC1345/46/47)
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
slave
AHB TO APB
BRIDGE
USART/
SMARTCARD INTERFACE
12-bit ADC
I
2
C-BUS
16-bit COUNTER/TIMER 0
SSP0
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
SYSTEM CONTROL
WINDOWED WATCHDOG
TIMER
PMU
RI TIMER
GPIO PIN INTERRUPT
GPIO GROUP0 INTERRUPT
GPIO GROUP1 INTERRUPT
SSP1
IOCON
RXD
TXD
DCD , DSR
(1)
, RI
(1)
CTS, RTS, DTR
SCLK
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
(2)
CT16B1_MAT[1:0]
CT16B1_CAP[1:0]
(2)
CT32B0_MAT[3:0]
CT32B0_CAP[1:0]
(2)
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(2)
AD[7:0]
SCL, SDA
SCK0, SSEL0,
MISO0, MOSI0
SCK1, SSEL1,
MISO1, MOSI1
GPIO pins
GPIO pins
GPIO pins
002aag241
(1) Available on LQFP48 and LQFP64 packages only.
(2) CT16B0_CAP1, CT16B1_CAP1, CT32B1_CAP1 inputs available on LQFP64 packages only. CT32B0_CAP0 input available on
LQFP48 and LQFP64 packages only.
Fig 1.
Block diagram
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
5 of 77
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