Data Sheet
FEATURES
Triple 1800 mA Buck Regulator with
Precision Enables and Power-Good Outputs
ADP5135
TYPICAL APPLICATION CIRCUIT
ADP5135
3.0V
TO
5.5V
AVIN
C7
0.1µF
C1
10µF
ON
OFF
17
18
16
14
12
13
Input voltage range: 3.0 V to 5.5 V
Three 1800 mA buck regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx pins
Precision enables for easier power sequencing
Power-good pins for monitoring each regulator
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2/BUCK3: output voltage range from 0.8 V to 3.8 V
HOUSE-
KEEPING
10
15
AGND
VIN1
PGND1
EN1
V
DDIO
VOUT1
SW1
FB1
L1 1µH
R1
R2
MODE
VOUT2
SW2
FB2
L2 1µH
R3
R4
C4
22µF
PWM
AUTO
BUCK1
1.8A
11
C2
22µF
VIN2
C3
10µF
ON
OFF
3
5
PGND2
EN2
9
APPLICATIONS
Power for processors, application specific integrated circuits
(ASICs), field-programmable gate arrays (FPGAs), and
radio frequency (RF) chipsets
Portable instrumentation and medical devices
Space constrained devices
BUCK2
1.8A
4
8
7
VIN3
C5
10µF
ON
OFF
21
19
22
VOUT3
SW3
FB3
L3 1µH
R5
R6
C6
22µF
V
DDIO
R7
100Ω
PGND3
EN3
BUCK3
1.8A
20
23
24
POWER
GOOD
6
2
1
PG1
PG2
PG3
R8
100Ω
Figure 1.
GENERAL DESCRIPTION
The
ADP5135
combines three high performance buck regulators
(BUCK1, BUCK2, and BUCK3). It is available in a 24-lead,
4 mm × 4 mm LFCSP.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced pulse-width modulation (PWM) mode. When the
MODE pin is set to low, the buck regulators operate in PWM
mode only when the load is above a predefined threshold. When
the load current falls below this predefined threshold, the
regulator operates in power save mode (PSM), improving the
light load efficiency.
BUCK1 and BUCK2 operate in synchronization, and BUCK3
operates out of phase to reduce the input capacitor requirement.
Regulators in the
ADP5135
are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
Rev. 0
Document Feedback
Table 1. Family Devices
Device
ADP5023
ADP5024
ADP5034
ADP5037
ADP5033
ADP5040
ADP5041
Channels
2 buck regulators, 1 LDO
2 buck regulators, 1 LDO
2 buck regulators, 2 LDOs
2 buck regulators, 2 LDOs
2 buck regulators, 2 LDOs
with 2 ENx pins
1 buck regulator, 2 LDOs
1 buck regulator, 2 LDOs
with supervisory circuit,
watchdog function, and
manual reset
2 buck regulators with
2 ENx pins
2 buck regulators, 2 LDOs
with precision enable and
power good
Max
Current
800 mA,
300 mA
1.2 A,
300 mA
1.2 A,
300 mA
800 mA,
300 mA
800 mA,
300 mA
1.2 A,
300 mA
1.2 A,
300 mA
Package
LFCSP (CP-24-10)
LFCSP (CP-24-10)
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
WLCSP (CB-16-8)
LFCSP (CP-20-10)
LFCSP (CP-20-10)
ADP5133
ADP5134
800 mA
1.2 A,
300 mA
WLCSP (CB-16-8)
LFCSP (CP-24-7)
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
12604-001
R9
100Ω
ADP5135
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
BUCK1, BUCK2, and BUCK3 .................................................... 4
Input and Output Capacitors, Recommended ......................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Data Sheet
Theory of Operation ...................................................................... 13
Power Management Unit........................................................... 13
Buck Regulators: BUCK1, BUCK2, AND BUCK3 ................ 15
Applications Information .............................................................. 17
Buck External Component Selection....................................... 17
Typical Application Schematics................................................ 19
Power Dissipation and Thermal Considerations ....................... 21
Buck Regulator Power Dissipation .......................................... 21
Junction Temperature ................................................................ 22
PCB Layout Guidelines .................................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
11/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
SPECIFICATIONS
ADP5135
V
AVIN
= V
IN1
= V
IN2
= V
IN3
= 3.0 V to 5.5 V; T
J
= −40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
START-UP TIME
1
BUCK1
BUCK2
BUCK3
START-UP TIME, BUCK3 FIRST
BUCK3
BUCK1
BUCK2
SHUTDOWN CONTROL
Level High
Level Low
PRECISION ENABLE PINS
Analog Activation Threshold
Hysteresis (Regulator Deactivation)
Input Leakage Current
POWER-GOOD PINS
Falling Threshold
Rising Threshold
Delay
Leakage Current
Output Voltage Low
MODE PIN
Level High
Level Low
INPUT CURRENT
All Channels Enabled
All Channels Disabled
AVIN UNDERVOLTAGE LOCKOUT
Mid UVLO Input Voltage Rising
Mid UVLO Input Voltage Falling
1
Symbol
V
AVIN
, V
IN1
,
V
IN2
, V
IN3
TS
SD
TS
SD_HYS
t
START1
t
START2
t
START3
t
START4
t
START5
t
START6
Test Conditions/Comments
Min
3.0
Typ
Max
5.5
Unit
V
T
J
rising
150
20
450
550
550
550
200
300
°C
°C
μs
μs
μs
μs
μs
μs
V
0.35
V
V
mV
μA
% V
OUT
% V
OUT
μs
μA
V
V
V
μA
μA
V
V
All ENx pins below V
IL_EN
level to achieve I
SHUTDOWN
V
IH_EN
V
IL_EN
V
ENR
V
ENH
V
I-LEAKAGE
V
PGLOW
V
PGHYS
t
PGDLY
I
PGIQ
V
PGOL
V
IH_MOD
V
IL_MOD
No load, no buck switching
I
STBY_NOSW
I
SHUTDOWN
UVLO
AVINRISE
UVLO
AVINFALL
T
J
= −40°C to +85°C
85
0.3
110
1.5
2.95
2.45
Regulator activation/deactivation thresholds
Device out of shutdown (V
ENx
> V
IH_EN
)
0.9
0.94
0.97
80
0.05
85
94
20
0.02
1
1
Monitors V
OUT
falling out of regulation
91
V
PG
= V
IN
Load current = 1 mA
1.1
0.4
97
1
0.15
Start-up time is defined as the time from EN1 = EN2 = EN3 at 0 V to V
AVIN
to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are shorter
for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 24
ADP5135
BUCK1, BUCK2, AND BUCK3
Data Sheet
V
AVIN
= V
IN1
= V
IN2
= V
IN3
= 3.0 V to 5.5 V; T
J
= −40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for typical
specifications, unless otherwise noted.
1
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
Line Regulation
Symbol
ΔV
OUT1
/V
OUT1
, ΔV
OUT2
/V
OUT2
,
ΔV
OUT3
/V
OUT3
(ΔV
OUT1
/V
OUT1
)/ΔV
IN1
,
(ΔV
OUT2
/V
OUT2
)/ΔV
IN2
,
(ΔV
OUT3
/V
OUT3
)/ΔV
IN3
(ΔV
OUT1
/V
OUT1
)/ΔI
OUT1
,
(ΔV
OUT2
/V
OUT2
)/ΔI
OUT2
,
(ΔV
OUT3
/V
OUT3
)/ΔI
OUT3
V
FB1
, V
FB2
I
IN1
I
IN2
I
IN3
I
IN
I
PSM
R
NFET
R
PFET
R
NFET
R
PFET
I
LIMIT1
, I
LIMIT2
, I
LIMIT3
R
PWDN
f
SW
Test Conditions/Comments
PWM mode; I
LOAD1
= I
LOAD2
= I
LOAD3
= 0 mA
PWM mode
Min
−1.8
−0.05
Typ
Max
+1.8
Unit
%
%/V
Load Regulation
I
LOAD
= 0 mA to 1800 mA, PWM mode
−0.1
%/A
VOLTAGE FEEDBACK
OPERATING SUPPLY CURRENT
BUCK1 Only
BUCK2 Only
BUCK3 Only
BUCK1, BUCK2, and
BUCK3
PSM CURRENT THRESHOLD
SWx CHARACTERISTICS
SWx On Resistance
Models with adjustable outputs
MODE = ground
I
LOAD1
= 0 mA, device not switching, all
other channels disabled
I
LOAD2
= 0 mA, device not switching, all
other channels disabled
I
LOAD3
= 0 mA, device not switching, all
other channels disabled
I
LOAD1
= I
LOAD2
= I
LOAD3
= 0 mA, device
not switching
PSM to PWM operation
V
IN1
= V
IN2
= V
IN3
= 3.6 V
V
IN1
= V
IN2
= V
IN3
= 3.6 V
V
IN1
= V
IN2
= V
IN3
= 5.5 V
V
IN1
= V
IN2
= V
IN3
= 5.5 V
Positive channel field effect transistor
(PFET) switch peak current limit
VIN1 = VIN2 = VIN3 = 3.6 V; channel
disabled
0.491
0.5
42
52
52
85
100
140
190
122
147
2600
75
0.509
V
μA
μA
μA
μA
mA
Current Limit
ACTIVE PULL-DOWN
RESISTANCE
OSCILLATOR FREQUENCY
1
2250
225
295
189
228
2950
mΩ
mΩ
mΩ
mΩ
mA
Ω
2.5
3.0
3.5
MHz
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
INPUT AND OUTPUT CAPACITORS, RECOMMENDED
T
A
= −40°C to +125°C, unless otherwise specified.
Table 4.
Parameter
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS
BUCK1, BUCK2, and BUCK3
Input Capacitor Ratings
Output Capacitor Ratings
CAPACITOR ESR
Symbol
Min
Typ
Max
Unit
C
MIN1
, C
MIN2
, C
MIN3
C
MIN4
, C
MIN5
, C
MIN6
R
ESR
4.7
10
0.001
40
40
1
μF
μF
Ω
Rev. 0 | Page 4 of 24
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVIN to AGND
VIN1, VIN2, VIN3 to AVIN
PGND1, PGND2, PGND3 to AGND
VOUT1, VOUT2, VOUT3, FB1, FB2, FB3,
EN1, EN2, EN3, MODE, PG1, PG2, PG3
to AGND
SW1 to PGND1
SW2 to PGND2
SW3 to PGND3
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (AVIN + 0.3 V)
ADP5135
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
24-Lead LFCSP
θ
JA
35
θ
JC
3
Unit
°C/W
−0.3 V to (VIN1 + 0.3 V)
−0.3 V to (VIN2 + 0.3 V)
−0.3 V to (VIN3 + 0.3 V)
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
Rev. 0 | Page 5 of 24
Embedded System
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