PF4210
14-channel Power Management Integrated Circuit (PMIC) for
audio/video applications
Rev. 1.0 — 14 February 2018
Data sheet: technical data
1
General description
The PF4210 high performance power management integrated circuit (PMIC) provides
a highly programmable/configurable architecture with fully integrated power devices
and minimal external components. With up to six buck converters, six linear regulators,
an RTC supply, and a coin cell charger, the PF4210 can provide power for a complete
system, including applications processors, memory, and system peripherals, in a wide
range of applications.
With on-chip one-time programmable (OTP) memory, the PF4210 is available in
preprogrammed standard version or nonprogrammed to support custom programming.
The PF4210 is defined to power low-cost audio/video applications using the i.MX 8M
family of applications processors.
2
Features and benefits
•
Four to six buck converters, depending on configuration
–
Single/dual phase/parallel options
–
DDR termination tracking mode option
•
Boost regulator to 5.0 V output
•
Six general purpose linear regulators
•
Programmable output voltage, sequence, and timing
•
OTP (one-time programmable) memory for device configuration
•
Coin cell charger and RTC supply
•
DDR termination reference voltage
•
Power control logic with processor interface and event detection
2
•
I C control
•
Individually programmable on, off, and standby modes
NXP Semiconductors
14-channel Power Management Integrated Circuit (PMIC) for audio/video applications
PF4210
3
Simplified application diagram
VIN
EXTERNAL
REGULATOR
3.3 V, 8.0 A
EXTERNAL
REGULATOR
0.9 V
EXTERNAL
REGULATOR
0.9 V
i.MX 8M
PROCESSOR
CORTEX A53 PLATFORM
QUAD CORTEX-A53
L1 CACHE
L2 CONTROLLER AND SCU
L2 CACHE MEMORY
GPU
VPU
SOC (always ON)
PMIC
PF4210
SW1AB
0.9 V, 2.5 A
SW1C
0.9 V, 2.0 A
LOAD
SWITCH
SW4A
1.8 V, 1.0 A
VGEN4
1.8 V, 350 mA
DISPLAYMIX
3.3 V GPIO PAO
ENABLE
1.8 V GPIO PAO
eFuse
PLL
XTAL
TEMPERATURE SENSOR
SW3AB
1.0 V, 3.0 A
SW2
1.1 V, 2.5 A
VGEN3
1.8 V, 100 mA
DRAM CONTROLLER
DRAM PHY
LPDDR4
PCIe PHY
VGEN2
0.9 V, 250 mA
VGEN5
3.3 V, 100 mA
VSNVS 1.0 V,
1.5 mA or 1.0 mA
VGEN1
1.5 V, 100 mA
VGEN6
2.8 V, 200 mA
HDMI PHY
MIPI PHY
USB PHY1
USB PHY2
SNVS_LP
PMIC PAD
Camera
SD2
aaa-026470
Figure 1. Simplified application diagram
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 1.0 — 14 February 2018
2 / 141
NXP Semiconductors
14-channel Power Management Integrated Circuit (PMIC) for audio/video applications
PF4210
4
Applications
•
•
•
•
•
•
OTT STB
Wireless audio
Voice recognition assistant
A/V receivers
Sound bars
General embedded
5
Orderable parts
The PF4210 is available with both preprogrammed and nonprogrammed OTP memory
configurations. The nonprogrammed device uses A0 as the programming code. The
preprogrammed devices are identified using the program codes from
Table 1,
which also
list the associated NXP reference designs where applicable.
Details of the OTP programming for each device can be found in
Table 8.
Table 1. Orderable part variations
Part number
[1]
Temperature (T
A
) Package
0 °C to 85 °C (for
use in consumer
applications)
56 QFN 8x8 mm - 0.5 mm
pitch WF-type QFN (wettable
flank)
Programming
[2]
Reference designs
N/A
MCIMX8M-EVK
N/A
N/A
N/A
MCIMX8M-EVK
N/A
N/A
MC32PF4210A0ES
MC32PF4210A1ES
MC32PF4210A2ES
MC32PF4210A3ES
MC34PF4210A0ES
MC34PF4210A1ES
MC34PF4210A2ES
MC34PF4210A3ES
[1]
[2]
A0
(Nonprogrammed)
A1
A2
A3
−40 °C to 105 °C
(for use in industrial
applications)
A0
(Nonprogrammed)
A1
A2
A3
For tape and reel, add an R2 suffix to the part number.
For programming details see
Table 8.
The available OTP options are not restricted to the listed reference designs. They can be used in any application
where the listed voltage and sequence details are acceptable.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 1.0 — 14 February 2018
3 / 141
NXP Semiconductors
14-channel Power Management Integrated Circuit (PMIC) for audio/video applications
PF4210
6
Internal block diagram
VIN1
VGEN1
VGEN1
100 mA
VGEN2
250 mA
VGEN3
100 mA
VGEN4
350 mA
VGEN5
100 mA
VGEN6
200 mA
OTP
VDDOTP
SUPPLIES
CONTROL
CONTROL
SW3A/B
SINGLE/DUAL
DDR
3000 mA
BUCK
PF4210
SW1A/B
SINGLE/DUAL
2500 mA
BUCK
O/P
DRIVE
O/P
DRIVE
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
SW2
2500 mA
BUCK
O/P
DRIVE
SW2LX
SW2IN
SW2IN
SW2FB
SW3AFB
O/P
DRIVE
O/P
DRIVE
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
DVS CONTROL
SW4
1000 mA
BUCK
SW4FB
O/P
DRIVE
SW4IN
SW4LX
GNDREF1
VGEN2
VIN2
VGEN3
SW1C
2000 mA
BUCK
CORE CONTROL LOGIC
INITIALIZATION STATE
MACHINE
O/P
DRIVE
VGEN4
VIN3
VGEN5
VGEN6
VDDIO
SCL
SDA
I2C
INTERFACE
DVS
CONTROL
VCOREDIG
VCOREREF
VCORE
GNDREF
REFERENCE
GENERATION
TRIM-IN-PACKAGE
I2C REGISTER
MAP
CLOCKS
AND RESETS
SWBST
600 mA
BOOST
O/P
DRIVE
SWBSTLX
SWBSTIN
SWBSTFB
VREFDDR
VINREFDDR
VHALF
CLOCKS
32 kHz and 16 MHz
VIN
LI-CELL
CHARGER
LICELL
BEST
OF
SUPPLY
VSNVS
VSNVS
ICTEST
STANDBY
SDWNB
PWRON
RESETBMCU
INTB
aaa-026471
Figure 2. Simplified internal block diagram
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 1.0 — 14 February 2018
4 / 141
NXP Semiconductors
14-channel Power Management Integrated Circuit (PMIC) for audio/video applications
PF4210
7
Pinning information
7.1 Pinning
52
VCOREREF
PF4210
51
VCOREDIG
44
SWBSTFB
46
SWBSTLX
45
SWBSTIN
48
GNDREF
47
VDDOTP
49
VCORE
43
VSNVS
42
LICELL
41
VGEN6
40
VIN3
39
VGEN5
38
SW3AFB
37
SW3AIN
EP
36
SW3ALX
35
SW3BLX
34
SW3BIN
33
SW3BFB
32
SW3VSSSNS
31
VREFDDR
30
VINREFDDR
29
VHALF
56
PWRON
55
VDDIO
53
SDA
54
SCL
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
1
2
3
4
5
6
7
8
9
SW1BIN
10
SW1CLX
11
SW1CIN
12
SW1CFB
13
SW1VSSSNS
14
GNDREF1
15
VGEN1
16
VIN1
17
VGEN2
18
SW4FB
19
SW4IN
20
SW4LX
21
SW2LX
22
SW2IN
23
SW2IN
24
SW2FB
25
VGEN3
26
VIN2
27
VGEN4
28
50
VIN
Transparent top view
aaa-026472
Figure 3. Pinout diagram
7.2 Pin definitions
Table 2. Pin definitions
Number Name
1
2
3
4
5
6
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
[1]
Function
Output
Output
Output
Input
Input
Input
Max rating
3.6 V
3.6 V
3.6 V
3.6 V
7.5 V
3.6 V
Type
Digital
Digital
Digital
Digital
Digital/
Analog
Analog
Definition
Open drain interrupt signal to processor
Open drain signal to indicate an imminent system
shutdown
Open drain reset output to processor. Alternatively can be
used as a power output.
Standby input signal from processor
Reserved pin. Connect to GND in application.
Output voltage feedback for SW1A/B. Route this trace
separately from the high current path and terminate at the
output capacitance.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 1.0 — 14 February 2018
5 / 141
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