CYW4343W
Single-Chip 802.11 b/g/n MAC/Baseband/Radio
with Bluetooth 4.1
The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet
of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE
802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support. In addition, it integrates a power amplifier (PA) that meets the output
power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal
transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area.
The WLAN host interface supports SDIO v2.0 mode, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode
at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface.Using advanced design
techniques and process technology to reduce active and idle power, the CYW4343W is designed to address the needs of highly mobile
devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system
power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life.
The CYW4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms,
allowing for an extremely collaborative WLAN and Bluetooth coexistence.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM4343W
BCM4343WKUBG
CYW4343W
CYW4343WKUBG
■
Cypress Part Number
Features
IEEE 802.11x Key Features
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OneDriver™ software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as to
future devices.
Complies with Bluetooth Core Specification Version 4.1 with
provisions for supporting future specifications.
Bluetooth Class 1 or Class 2 transmitter operation.
Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets.
Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference.
Interface support — Host Controller Interface (HCI) using a
high-speed UART interface and PCM for audio data.
Low-power consumption improves battery life of handheld
devices.
Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
Automatic frequency detection for standard crystal and TCXO
values.
Single-band 2.4 GHz IEEE 802.11b/g/n.
Support for 2.4 GHz Cypress TurboQAM® data rates (256-
QAM) and 20 MHz channel bandwidth.
Integrated iTR switch supports a single 2.4 GHz antenna
shared between WLAN and Bluetooth.
Supports explicit IEEE 802.11n transmit beamforming
Tx and Rx Low-density Parity Check (LDPC) support for
improved range and power efficiency.
Supports standard SDIO v2.0 host interface.
Supports Space-Time Block Coding (STBC) in the receiver.
Integrated ARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field-upgrade with
future features. On-chip memory includes 512 KB SRAM and
640 KB ROM.
Bluetooth Features
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Cypress Semiconductor Corporation
Document Number: 002-14797 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 28, 2017
CYW4343W
General Features
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Supports a battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
Programmable dynamic power management.
4 Kbit One-Time Programmable (OTP) memory for storing
board parameters.
Can be routed on low-cost 1 x 1 PCB stack-ups.
74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA
package (4.87 mm × 2.87 mm, 0.4 mm pitch).
153-bump WLCSP package (115
μm
bump diameter, 180
μm
bump pitch).
Security:
❐
WPA and WPA2 (Personal) support for powerful encryption
and authentication.
❐
AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
❐
Reference WLAN subsystem provides Cisco Compatible Ex-
tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
❐
Reference WLAN subsystem provides Wi–Fi Protected Set-
up (WPS).
Worldwide regulatory support: Global products supported with
worldwide homologated design.
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Figure 1. CYW4343W System Block Diagram
VDDIO
VBAT
WL_REG_ON
WLAN
Host I/F
WL_IRQ
SDIO
CLK_REQ
BT_REG_ON
PCM
Bluetooth
Host I/F
BT_DEV_WAKE
BT_HOST_WAKE
UART
2.4 GHz WLAN +
Bluetooth TX/RX
CYW4343W
BPF
Document Number: 002-14797 Rev. *I
Page 2 of 103
CYW4343W
Contents
1. Overview ............................................................ 5
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
2.6
3.1
3.2
3.3
4.1
Overview ............................................................. 5
Features .............................................................. 6
Standards Compliance ........................................ 7
Power Supply Topology ...................................... 8
CYW4343W PMU Features ................................ 8
WLAN Power Management ............................... 11
PMU Sequencing .............................................. 11
Power-Off Shutdown ......................................... 12
Power-Up/Power-Down/Reset Circuits ............. 12
Crystal Interface and Clock Generation ............ 13
TCXO ................................................................ 13
External 32.768 kHz Low-Power Oscillator ....... 15
SDIO v2.0 .......................................................... 16
4.1.1 SDIO Pin Descriptions ........................... 16
MAC Features ................................................... 17
5.1.1 MAC Description .................................... 17
Figure 9..PSM ...................................................... 18
Figure 9..WEP ...................................................... 18
Figure 9..TXE ....................................................... 18
Figure 9..RXE ...................................................... 18
Figure 9..IFS ........................................................ 19
Figure 9..TSF ....................................................... 19
Figure 9..NAV ...................................................... 19
Figure 9..MAC-PHY Interface .............................. 19
PHY Description ................................................ 19
5.2.1 PHY Features ........................................ 20
Receive Path ..................................................... 22
Transmit Path .................................................... 22
Calibration ......................................................... 22
Features ............................................................ 23
Bluetooth Radio ................................................. 24
7.2.1 Transmit ................................................. 24
7.2.2 Digital Modulator .................................... 24
7.2.3 Digital Demodulator and Bit
Synchronizer .......................................... 24
7.2.4 Power Amplifier ..................................... 24
7.2.5 Receiver ................................................ 25
7.2.6 Digital Demodulator and Bit Synchronizer 25
7.2.7 Receiver Signal Strength Indicator ........ 25
8.7
8.8
8.9
8.5
8.6
8.1
8.2
8.3
8.4
7.2.8 Local Oscillator Generation ....................25
7.2.9 Calibration ..............................................25
8. Bluetooth Baseband Core.............................. 26
Bluetooth 4.1 Features .......................................26
Link Control Layer ..............................................26
Test Mode Support .............................................27
Bluetooth Power Management Unit ...................27
8.4.1 RF Power Management ..........................27
8.4.2 Host Controller Power Management ......27
BBC Power Management ...................................29
8.5.1 Wideband Speech ..................................29
Packet Loss Concealment .................................29
8.6.1 Codec Encoding .....................................30
8.6.2 Multiple Simultaneous A2DP Audio
Streams ..................................................30
Adaptive Frequency Hopping .............................30
Advanced Bluetooth/WLAN Coexistence ...........30
Fast Connection (Interlaced Page and Inquiry
Scans) ................................................................30
2. Power Supplies and Power Management ....... 8
3. Frequency References ................................... 13
4. WLAN System Interfaces ............................... 16
5. Wireless LAN MAC and PHY.......................... 17
5.1
9. Microprocessor and Memory Unit for Bluetooth
31
9.1
9.2
RAM, ROM, and Patch Memory .........................31
Reset ..................................................................31
10. Bluetooth Peripheral Transport Unit............. 32
10.1 PCM Interface ....................................................32
10.1.1 Slot Mapping ...........................................32
10.1.2 Frame Synchronization ...........................32
10.1.3 Data Formatting ......................................32
10.1.4 Wideband Speech Support .....................32
10.1.5 PCM Interface Timing .............................33
10.1.5.Short Frame Sync, Master Mode ...............33
Table 7..Short Frame Sync, Slave Mode ..............34
Table 8..Long Frame Sync, Master Mode .............35
Table 9..Long Frame Sync, Slave Mode ...............36
10.2 UART Interface ..................................................37
10.3 I
2
S Interface .......................................................38
10.3.1 I
2
S Timing ...............................................39
5.2
6. WLAN Radio Subsystem ................................ 21
6.1
6.2
6.3
7.1
7.2
7. Bluetooth Subsystem Overview .................... 23
11. CPU and Global Functions ............................ 41
11.1 WLAN CPU and Memory Subsystem ................41
11.2 One-Time Programmable Memory .....................41
11.3 GPIO Interface ...................................................41
11.4 External Coexistence Interface ..........................41
11.4.1 2-Wire Coexistence ................................42
11.4.2 3-Wire and 4-Wire Coexistence
Interfaces ................................................42
11.5 JTAG Interface ..................................................43
11.6 UART Interface .................................................43
Page 3 of 103
Document Number: 002-14797 Rev. *I
CYW4343W
12. WLAN Software Architecture......................... 44
12.1 Host Software Architecture ............................... 44
12.2 Device Software Architecture ............................ 44
12.3 Remote Downloader ......................................... 44
12.4 Wireless Configuration Utility ............................ 44
16. Bluetooth RF Specifications .......................... 78
17. Internal Regulator Electrical Specifications. 84
17.1 Core Buck Switching Regulator .........................84
17.2 3.3V LDO (LDO3P3) ..........................................85
17.3 CLDO .................................................................86
17.4 LNLDO ...............................................................87
13. Pinout and Signal Descriptions..................... 45
13.1 Ball Map ............................................................ 45
13.2 WLBGA Ball List in Ball Number Order with X-Y
Coordinates ....................................................... 47
13.3 WLCSP Bump List in Bump Order with X-Y
Coordinates ....................................................... 49
13.4 WLBGA Ball List Ordered By Ball Name ........... 54
13.5 WLCSP Bump List Ordered By Name .............. 55
13.6 Signal Descriptions ........................................... 57
13.7 WLAN GPIO Signals and Strapping Options .... 65
13.8 Chip Debug Options .......................................... 65
13.9 I/O States .......................................................... 66
18. System Power Consumption ......................... 88
18.1 WLAN Current Consumption ..............................88
18.1.1 2.4 GHz Mode ........................................88
18.2 Bluetooth Current Consumption .........................89
19. Interface Timing and AC Characteristics ..... 90
19.1 SDIO Default Mode Timing ................................90
19.2 SDIO High-Speed Mode Timing .........................91
19.3 JTAG Timing ......................................................92
20. Power-Up Sequence and Timing................... 93
20.1 Sequencing of Reset and Regulator Control
Signals ...............................................................93
20.1.1 Description of Control Signals ................93
20.1.2 Control Signal Timing Diagrams .............94
14. DC Characteristics.......................................... 68
14.1 Absolute Maximum Ratings .............................. 68
14.2 Environmental Ratings ...................................... 68
14.3 Electrostatic Discharge Specifications .............. 69
14.4 Recommended Operating Conditions and DC
Characteristics .................................................. 69
21. Package Information ...................................... 96
21.1 Package Thermal Characteristics ......................96
21.1.1 Junction Temperature Estimation and
PSI Versus Theta
jc
..................................96
15. WLAN RF Specifications ................................ 71
15.1 2.4 GHz Band General RF Specifications ......... 71
15.2 WLAN 2.4 GHz Receiver Performance
Specifications .................................................... 72
15.3 WLAN 2.4 GHz Transmitter Performance
Specifications .................................................... 75
15.4 General Spurious Emissions Specifications ...... 77
22. Mechanical Information.................................. 97
23. Ordering Information.................................... 101
24. Additional Information ................................. 101
24.1 Acronyms and Abbreviations ...........................101
24.2 IoT Resources ..................................................101
Document History Page ............................................... 102
Sales, Solutions, and Legal Information .................... 103
Document Number: 002-14797 Rev. *I
Page 4 of 103
CYW4343W
1. Overview
1.1 Overview
The Cypress CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor
solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is
designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2
shows the interconnection of all the major physical blocks in the CYW4343W and their associated external interfaces, which are described in greater detail in
subsequent sections.
Figure 2. CYW4343W Block Diagram
C o rte x
M3
AHB
JTAG*
ETM
SDP
Debug
AHB Bus Matrix
A H B
t
o
A
P B
B r id g e
APB
W D
T
im e r
S W
T
im e r
G P IO
C trl
RAM
ROM
P a tch
In t e r C t r l
DM A
B u s
A
r b
A R M
IP
J T A G
s
u p p o r t e d
o
v e r
S
D IO
o
r
B
T
P
C M
S D IO
SW REG
LD O x2
LPO
X T A L
O
S C .
POR
Pow er
S u p p ly
S le e p
C
L K
XTAL
W L_REG _O N
BPL
B u ffe r
APU
B T
C
lo c k /
Hopper
B lu e R F
In t e r fa c e
LC U
Debug
UART
D ig it a l
I/ O
I/O Port Control
M odem
D ig it a l
D e m o d .
&
B
it
Sync
RF
PA
Common and
Radio Digital
D ig it a l
M od.
UART
S D IO
PM U
C o n tro l
R X /TX
B u ffe r
JTAG*
ARM
CM 3
Backplane
W DT
O TP
G P IO
UART
JT A G *
G P IO
UART
S u p p o r t e d
o
v e r
S
D IO
o
r
B
T
P
C M
I
2
S / P C M
RAM
G P IO
B T
P
H Y
IF
PLL
W ake/
S
W iM
p
x
C
t r l
x
le e
a
C o e
B T
C
lo c k
C
o n t r o l
S le e p
‐
t im e
K e e p in g
LPO
C lo c k
M anagem ent
XO
B u ffe r
PM U
PM U
C trl
B T
‐
W LA N
ECI
ROM
IEEE 802.11a/b/g/n
LNPPHY
Radio
MAC
2 . 4
G
H z
PA
2.4 GHz
S h a r e d
L
N A
W iM a x
Coex.
PTU
BPF
POR
W LA N
VBAT
XTAL
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D I O
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Document No. 002-14797 Rev. *I
BT_REG_ON
VREGs
Page 5 of 103
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