DS1801
Dual Audio Taper Potentiometer
www.dalsemi.com
FEATURES
Ultra-low power consumption
Operates from 3V or 5V supplies
Two digitally controlled, 65-position
potentiometers including mute
Logarithmic resistive characteristics (1 dB
per step)
Zero-crossing detection eliminates noise
caused by wiper movement
Serial port provides means for setting and
reading both potentiometers wipers
14-pin PDIP, 16-pin SOIC, and 14-pin
TSSOP packages
Operating Temperature Range:
- Industrial: -40°C to +85°C
Software mute
Resistance available: 45 kΩ
PIN ASSIGNMENT
GND
COUT
RST
ZCEN
W0
L0
H0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
CLK
D
AGND
H1
L1
W1
DS1801 14-Pin PDIP (300-mil)
DS1801 14-Pin TSSOP (173-mil)
GND
COUT
RST
ZCEN
NC
W0
L0
H0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
CLK
D
NC
AGND
H1
L1
W1
PIN DESCRIPTION
L0, L1
H0, H1
W0,W1
V
CC
RST
D
CLK
GND
AGND
ZCEN
C
OUT
NC
-
-
-
-
-
-
-
-
-
-
-
-
Low End of Resistor
High End of Resistor
Wiper End of Resistor
3V or 5V Power Supply Input
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Digital Ground
Analog Ground
Zero-Crossing Detect Input
Cascade Output
No Connect
DS1801S 16-PIN SOIC (300-mil)
See Mech. Drawings Section
DESCRIPTION
The DS1801 is a dual audio taper potentiometer having logarithmic resistive characteristics over the
device range. Each potentiometer provides 65 wiper positions with a 1 dB increment per step and device
mute. The 3-wire serial interface, using a CPU, provides the user the ability of reading or writing exact
wiper positions of the two potentiometers. Additionally, the part contains a zero-crossing detection
feature that minimizes noise resulting from wiper transitions. Packages for the part include a 14-pin
PDIP, 16-pin SOIC, and 14-pin TSSOP.
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030300
DS1801
OPERATION
The DS1801 provides two 65-position potentiometers per package, each having a logarithmic resistive
characteristic as shown in Table 1. The DS1801 is controlled by a 3-wire serial interface. The 3-wire
serial interface is designed for CPU-controlled applications and allows the potentiometer’s exact wiper
position to be read or written. The DS1801 design supports daisy-chaining for multi-device
environments.
Figure 1 presents a block diagram of the DS1801. As shown, the inputs from the 3-wire serial interface
drive a command/control unit. The command/control unit interprets these inputs for control of the two
potentiometers.
On power-up, the serial port is stable and active within 10 microseconds. The wiper position on power-up
will be at position 63, the low end of the potentiometer. Position 64 is the mute level.
RESISTANCE CHARACTERISTICS
Table 1
POSITION
0
1
2
3
4
5
OUTPUT LEVEL (dB)
0
-1
-2
-3
-4
-5
63
64(mute)
-63
<-90
DS1801 BLOCK DIAGRAM
Figure 1
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DS1801
3-WIRE SERIAL INTERFACE CONTROL
Communication and control of the DS1801 is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface is designed for microprocessor or
microcontroller applications. The interface consists of three input signals which include
RST
, CLK and
D.
The
RST
control signal is used to enable 3-wire serial port write operations. The CLK terminal is a clock
signal input that provides synchronization for data I/O while the D signal input serves to transfer
potentiometer wiper position settings to the device.
As shown in Figure 3, a 3-wire serial port operation begins with a transition of the
RST
signal input to a
high state. Once the 3-wire port has been activated, data is clocked into the part on the low to high
transition of the CLK signal input. Data input via the D line is transferred in the order of the desired
potentiometer-0 value followed by the potentiometer-1 value.
The DS1801 contains two 65-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to the 16-bit I/O shift register which is used to store wiper position
during powered conditions. Because the potentiometer has 65-positions, only 7 bits of data are needed to
set wiper position. A detailed diagram of the 16-bit I/O shift register is shown in Figure 2. Bits 0 through
7 are reserved for the potentiometer-0 control while bits 8 through 15 are reserved for control of
potentiometer-1.
Bits 0 through 5 are used for actual wiper positioning of potentiometer-0. Bit 6 is used to mute
potentiometer-0. If this bit has value 1, the potentiometer-0 wiper will be connected to the low end of the
resistive array the mute position. The value of bit 7 is a “don’t care” and will not affect operation of the
DS1801 or potentiometer-0.
Bits 8 through 13 are used for wiper positioning of potentiometer-1. Bit 14 is used for muting of the
potentiometer-1 wiper output. Bit 15, like bit 7, is a “don’t care” and will not affect operation of the
DS1801.
Data for the DS1801 is transmitted LSB first starting with bit 0. A complete transmission of 16 bits of
data is required to insure proper setting of each potentiometer’s wiper. An incomplete transmission may
result in undesired wiper settings.
Once the complete 16 bits of information has been transmitted and the
RST
signal input transitions to a
low state, the new wiper positions are loaded into the part.
16-BIT I/O SHIFT REGISTER
Figure 2
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DS1801
TIMING DIAGRAMS
Figure 3
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DS1801
CASCADE OPERATION
A feature of the DS1801 is the ability to control multiple devices from a single processor. Multiple
DS1801s can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1801, bit 0 of the I/O shift register will appear at the C
OUT
output after a maximum delay
of 50 nanoseconds.
The C
OUT
output of the DS1801 can be used to drive the D input of another DS1801. When connecting
multiple devices, the total number of bits sent is always 16 times the number of DS1801s in the daisy
chain.
An optional feedback resistor can be placed between the C
OUT
terminal of the last device and the D input
of the first DS1801 thus allowing the controlling processor to read as well as write data or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2 to 10 kohms.
When reading data via the C
OUT
pin and isolation resistor, the D line is left floating by the reading device.
When
RST
is driven high, bit 0 is present on the C
OUT
pin, which is fed back to the input D pin through
the isolation resistor. When the CLK input transitions low to high, bit 0 is loaded into the first position of
the I/O shift register and bit 1 becomes present on C
OUT
and D of the next device. After 16 bits (or 16
times the number of DS1801s in the daisy chain), the data has shifted completely around and back to its
original position. When
RST
transitions to the low state to end data transfer, the value (the same as before
the read occurred) is loaded into wiper-0 and wiper-1.
CASCADING MULTIPLE DEVICES
Figure 4
Zero-Crossing Detection
The DS1801 provides a zero-crossing detection capability that minimizes any audible noise that may
result from sizable discrete wiper transitions when using the part in audio applications. The zero-crossing
detect feature allows independent wiper changes only when the two terminals of the potentiometer have
equal potentials and are within a 50 ms time window from the fall of the
RST
signal. If at 50 ms the
DS1801 has not detected a zero-crossing, the wiper position of the potentiometer(s) will change
regardless of the state of the input signal. Zero-crossing detection is activated when the
ZCEN
input level
is in a low-state. When high, the
ZCEN
input deactivates both the 50 ms time requirement and zero
detection crossing.
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