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100328QC

Description
Low Power Octal ECL/TTL Bi-Directional Translator with Latch
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size141KB,14 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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100328QC Overview

Low Power Octal ECL/TTL Bi-Directional Translator with Latch

100328QC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeLCC
package instructionQCCJ, LDCC28,.5SQ
Contacts28
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
maximum delay5.4 ns
Interface integrated circuit typeTTL TO ECL TRANSCEIVER
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.43 mm
Number of digits1
Number of functions8
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristics3-STATE
Output latch or registerLATCH
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5,-4.5 V
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyECL
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.43 mm
Base Number Matches1
100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch
April 1989
Revised August 2000
100328
Low Power Octal ECL/TTL Bi-Directional Translator
with Latch
General Description
The 100328 is an octal latched bi-directional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of this translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. A HIGH on the latch
enable input (LE) latches the data at both inputs even
though only one output is enabled at the time. A LOW on
LE makes the 100328 transparent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is
2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100328 is designed with FAST
TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 k
pull-down resistors.
Features
s
Identical performance to the 100128 at 50% of the
supply current
s
Bi-directional translation
s
2000V ESD protection
s
Latched outputs
s
FAST TTL outputs
s
3-STATE outputs
s
Voltage compensated operating range
= −
4.2V to
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100328SC
100328PC
100328QC
100328QI
Package Number
M24B
N24E
V28A
V28A
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
E
0
–E
7
T
0
–T
7
OE
LE
DIR
Description
ECL Data I/O
TTL Data I/O
Output Enable Input
Latch Enable Input
Direction Control Input
All pins function at 100K ECL levels except for T
0
–T
7
.
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010219
www.fairchildsemi.com

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