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JM38510/11106BCC

Description
SPDT, 1 Func, 1 Channel, JFET, CDIP14, SIDE BRAZED, DIP-14
CategoryThe signal circuit   
File Size105KB,9 Pages
ManufacturerHarris
Websitehttp://www.harris.com/
Download Datasheet Parametric View All

JM38510/11106BCC Overview

SPDT, 1 Func, 1 Channel, JFET, CDIP14, SIDE BRAZED, DIP-14

JM38510/11106BCC Parametric

Parameter NameAttribute value
MakerHarris
package instructionDIP,
Reach Compliance Codeunknown
Is SamacsysN
Other featuresFAULT PROTECTED
Analog Integrated Circuits - Other TypesSPDT
JESD-30 codeR-CDIP-T14
length18.54 mm
Nominal Negative Supply Voltage (Vsup)-15 V
Number of channels1
Number of functions1
Number of terminals14
Nominal off-state isolation50 dB
Maximum on-state resistance (Ron)75 Ω
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Certification statusNot Qualified
Filter levelMIL-M-38510
Maximum seat height4.44 mm
Nominal supply voltage (Vsup)15 V
surface mountNO
Maximum disconnect time130 ns
Maximum connection time250 ns
technologyJFET
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
DG186/187/188
Vishay Siliconix
High-Speed Drivers with SPDT JFET Switches
FEATURES
D
Constant On-Resistance Over
Entire Analog Range
D
Low Leakage
D
Low Crosstalk
D
Rad Hardness
BENEFITS
D
D
D
D
D
Low Distortion
Eliminates Large Signal Errors
High Precision
High Bandwidth Capability
Fault Protection
APPLICATIONS
D
D
D
D
D
Audio Switching
Video Switching
Sample/Hold
Guidance and Control Systems
Telemetry
DESCRIPTION
The DG186/187/188 are precision single-pole, double-throw
(SPDT) analog switches designed to provide accurate
switching of video and audio signals. This series is ideally
suited for applications requiring a constant on-resistance over
the entire analog range.
on-resistance include audio switching, video switching, and
data acquisition.
The major difference in the devices is the on-resistance
(DG186—10
W
, DG187—30
W
, DG188—75
W).
Reduced
errors are achieved through low leakage current (I
D(on)
< 2 nA). Applications which benefit from the flat JFET
To achieve fast and accurate switch performance, each device
comprises two n-channel JFET transistors and a TTL
compatible bipolar driver. The driver is designed to achieve
break-before-make switching action, eliminating the
inadvertent shorting between channels and the crosstalk
which would result. In the on state, each switch conducts
current equally well in either direction. In the off condition, the
switches will block up to 20 V peak-to-peak, with feedthrough
of less than –60 dB at 10 MHz.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
NC
NC
NC
D
1
S
1
IN
V+
V
L
1
2
3
4
5
6
7
Dual-In-Line
Top View
14
13
12
11
10
9
8
NC
NC
D2
S
2
NC
V–
NC
D
1
S
1
IN
V+
V
L
1
2
3
4
5
6
7
Flat
Package
Top View
14
13
12
11
10
9
8
NC
NC
D
2
S
2
NC
V–*
V
R
IN
3
4
S
1
2
D
1
D
2
10
1
9
S
2
NC
8
7
Metal Can
Top View
5
V
L
6
V
R
V–*
Refer to JAN38510 Information, Military Section
V
R
V+
*COMMON TO SUBSTRATE AND CASE
TRUTH TABLE
Logic
0
1
SW
1
OFF
ON
Logic “0”
v
0.8 V
0
Logic “1”
w
2.0 V
20
SW
2
ON
OFF
Document Number: 70033
S-52895—Rev. E, 16-Jun-97
www.vishay.com
S
FaxBack 408-970-5600
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