19-1002; Rev 0; 8/04
KIT
ATION
EVALU
E
BL
AVAILA
12-Bit, 80Msps, 3.3V ADC
General Description
Features
♦
Excellent Dynamic Performance
68.2dB/68.0dB SNR at f
IN
= 3MHz/70MHz
89.3dBc/85.1dBc SFDR at f
IN
= 3MHz/70MHz
♦
3.3V Low-Power Operation
373mW (Single-Ended Clock Mode)
399mW (Differential Clock Mode)
3µW (Power-Down Mode)
♦
Differential or Single-Ended Clock
♦
Fully Differential or Single-Ended Analog Input
♦
Adjustable Full-Scale Analog Input Range: ±0.35V
to ±1.15V
♦
Common-Mode Reference
♦
CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦
Data-Valid Indicator Simplifies Digital Design
♦
Data Out-of-Range Indicator
♦
Miniature, 40-Pin Thin QFN Package with Exposed
Paddle
♦
Evaluation Kit Available (Order MAX1211EVKIT)
MAX1208
The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts single-
ended or differential signals. The MAX1208 is optimized
for low power, small size, and high dynamic performance
in baseband applications.
Powered from a single 3.0V to 3.6V supply, the
MAX1208 consumes only 373mW while delivering a
typical signal-to-noise (SNR) performance of 68.2dB at
an input frequency of 32.5MHz. In addition to low oper-
ating power, the MAX1208 features a 3µW power-down
mode to conserve power during idle periods.
A flexible reference structure allows the MAX1208 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.15V. The MAX1208 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX1208 supports both a single-ended and differ-
ential input clock drive. Wide variations in the clock
duty cycle are compensated with the ADC’s internal
duty-cycle equalizer (DCE).
ADC conversion results are available through a 12-bit,
parallel, CMOS-compatible output bus. The digital out-
put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminates
external components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX1208 to interface with various logic levels.
The MAX1208 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the
Pin-Compatible Versions
table for a complete
family of 14-bit and 12-bit high-speed ADCs.
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
40 Thin QFN
(6mm x 6mm x
0.8mm)
PKG
CODE
T4066-3
MAX1208ETL
-40°C to +85°C
Pin-Compatible Versions
PART
MAX12553
MAX1209
MAX1211
MAX1208
MAX1207
MAX1206
SAMPLING
RATE (Msps)
65
80
65
80
65
40
RESOLUTION
(BITS)
14
12
12
12
12
12
TARGET
APPLICATION
IF/Baseband
IF
IF
Baseband
Baseband
Baseband
Applications
Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
Ultrasound and Medical Imaging
Portable Instrumentation
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 80Msps, 3.3V ADC
MAX1208
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ...........................................................-0.3V to +3.6V
OV
DD
to GND........-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
INP, INN to GND ...-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN,
COM to GND ......-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND ........-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
D11 Through D0 I.C., DAV, DOR to GND ...-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V
IN
= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T
= low, f
CLK
= 80MHz (50% duty cycle), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
(Note 2)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
Input Capacitance
(Figure 3)
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Data Latency
Figure 6
8.5
f
CLK
80
5
MHz
MHz
Clock
cycles
dBFS
dB
C
PAR
C
SAMPLE
Fixed capacitance to ground
Switched capacitance
V
DIFF
Differential or single-ended inputs
±1.024
V
DD
/ 2
2
1.9
V
V
pF
INL
DNL
f
IN
= 20MHz
f
IN
= 20MHz, no missing codes over
temperature
V
REFIN
= 2.048V
V
REFIN
= 2.048V
-0.83
12
±0.65
±0.35
±0.25
±1.0
±0.92
±5.6
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
(differential inputs, Note 2)
Small-Signal Noise Floor
Signal-to-Noise Ratio
SSNF
SNR
Input at less than -35dBFS
f
IN
= 3MHz at -0.5dBFS
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 3MHz at -0.5dBFS
Signal-to-Noise and Distortion
SINAD
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
65.2
65.4
-68.8
68.2
68.2
68.0
68.1
68.1
67.8
dB
2
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V
IN
= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, f
CLK
= 80MHz (50% duty cycle), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Spurious-Free Dynamic Range
SYMBOL
SFDR
CONDITIONS
fIN = 3MHz at -0.5dBFS
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
Total Harmonic Distortion
THD
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
Second Harmonic
HD2
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
fIN = 3MHz at -0.5dBFS
Third Harmonic
HD3
fIN = 32.5MHz at -0.5dBFS
fIN = 70MHz at -0.5dBFS
Intermodulation Distortion
Third-Order Intermodulation
Two-Tone Spurious-Free
Dynamic Range
Aperture Delay
Aperture Jitter
Output Noise
Overdrive Recovery Time
IMD
IM3
SFDRTT
tAD
tAJ
nOUT
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
Figure 4
Figure 4
INP = INN = COM
±10% beyond full scale
78.7
MIN
TYP
89.3
88.2
85.1
-87.1
-85.0
-81.2
-93
-89
-86.5
-96.8
-95.1
-85.1
-81.1
-84.4
85.4
0.9
<0.2
0.52
1
dBc
dBc
dBc
ns
psRMS
LSBRM
Clock
cycles
2.079
V
V
V
mV/mA
ppm/°C
mA
dBc
dBc
-77.2
dBc
dBc
MAX
UNITS
MAX1208
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)
REFOUT Output Voltage
COM Output Voltage
Differential Reference Output
REFOUT Load Regulation
REFOUT Temperature Coefficient
REFOUT Short-Circuit Current
TCREF
Short to VDD—sinking
Short to GND—sourcing
VREFOUT
VCOM
VREF
VDD / 2
VREF = VREFP - VREFN
1.978
2.048
1.65
1.024
35
+50
0.24
2.1
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated
internally)
REFIN Input Voltage
REFP Output Voltage
VREFIN
VREFP
(VDD/2) + (VREFIN / 4)
2.048
2.162
V
V
_______________________________________________________________________________________
3
12-Bit, 80Msps, 3.3V ADC
MAX1208
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V
IN
= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, f
CLK
= 80MHz (50% duty cycle), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
REFN Output Voltage
COM Output Voltage
Differential Reference Output
Voltage
Differential Reference
Temperature Coefficient
REFIN Input Resistance
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
Differential Reference Input
Voltage
REFP Sink Current
REFN Source Current
COM Sink Current
REFP, REFN Capacitance
COM Capacitance
CLOCK INPUTS
(CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
Differential Input Voltage Swing
Differential Input Common-Mode
Voltage
Input Resistance
Input Capacitance
DIGITAL INPUTS
(CLKTYP, G/T, PD)
Input High Threshold
V
IH
0.8 x
OV
DD
V
R
CLK
C
CLK
V
IH
V
IL
CLKTYP = GND, CLKN = GND
CLKTYP = GND, CLKN = GND
CLKTYP = high
CLKTYP = high
Figure 5
1.4
V
DD
/ 2
5
2
0.8 x
V
DD
0.2 x
V
DD
V
V
V
P-P
V
kΩ
pF
V
REF
I
REFP
I
REFN
I
COM
V
COM
V
DD
/ 2
V
REFP
- V
COM
V
REFN
- V
COM
V
REF
= V
REFP
- V
REFN
V
REFP
= 2.162V
V
REFN
= 1.138V
SYMBOL
V
REFN
V
COM
V
REF
V
DD
/ 2
V
REF
= V
REFP
- V
REFN
CONDITIONS
(V
DD
/ 2) - (V
REFIN
/ 4)
1.60
0.969
MIN
TYP
1.138
1.65
1.024
±25
>50
1.65
0.512
-0.512
1.024
1.1
1.1
0.3
13
6
1.70
1.069
MAX
UNITS
V
V
V
ppm/°C
MΩ
V
V
V
V
mA
mA
mA
pF
pF
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V
REFP
, V
REFN
, and V
COM
are applied externally)
4
_______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V
IN
= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, f
CLK
= 80MHz (50% duty cycle), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Input Low Threshold
Input Leakage Current
Input Capacitance
C
DIN
D11–D0, DOR, I
SINK
= 200µA
DAV, I
SINK
= 600µA
D11–D0, DOR, I
SOURCE
= 200µA
Output Voltage High
V
OH
DAV, I
SOURCE
= 600µA
Tri-State Leakage Current
D11–D0, DOR Tri-State Output
Capacitance
DAV Tri-State Output
Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Output Supply Voltage
V
DD
OV
DD
Normal operating mode,
f
IN
= 32.5MHz at -0.5dBFS,
CLKTYP = GND, single-ended clock
Analog Supply Current
I
VDD
Normal operating mode,
f
IN
= 32.5MHz at -0.5dBFS,
CLKTYP = OV
DD,
differential clock
Power-down mode clock idle, PD = OV
DD
Normal operating mode,
f
IN
= 32.5MHz at -0.5dBFS,
CLKTYP = GND, single-ended clock
Analog Power Dissipation
P
DISS
Normal operating mode,
f
IN
= 32.5MHz at -0.5dBFS,
CLKTYP = OV
DD
, differential clock
Power-down mode clock idle, PD = OV
DD
3.0
1.7
3.3
2.0
3.6
V
DD
+
0.3V
V
V
I
LEAK
C
OUT
C
DAV
(Note 3)
(Note 3)
(Note 3)
3
6
OV
DD
-
0.2
V
OV
DD
-
0.2
±5
µA
pF
pF
SYMBOL
V
IL
V
IH
= OV
DD
V
IL
= 0
5
0.2
0.2
CONDITIONS
MIN
TYP
MAX
0.2 x
OV
DD
±5
±5
UNITS
V
µA
pF
MAX1208
DIGITAL OUTPUTS
(D11–D0, DAV, DOR)
Output Voltage Low
V
OL
V
113
mA
121
0.001
373
mW
399
0.003
436.3
132.2
_______________________________________________________________________________________
5
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