1032E-125LJ datasheet, PDF - EEWORLD Datasheet

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1032E-125LJ: DescriptionEE PLD, 12.5 ns, PQFP100; Categorysemiconductor Programmable logic devices; File Size153KB，16 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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1032E-125LJ Overview

EE PLD, 12.5 ns, PQFP100

1032E-125LJ Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Rated supply voltage	5 V
Number of input and output buses	64
Processing package description	TQFP-100
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
organize	2 DEDICATED INPUTS, 64 I/O
Maximum FCLK clock frequency	71 MHz
Output function	MACROCELL
Programmable logic type	EE PLD
propagation delay TPD	12.5 ns
Dedicated input quantity	2

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ispLSI and pLSI 1032E

High-Density Programmable Logic

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 125 MHz Maximum Operating Frequency

—

= 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— In-System Programmable (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispEXPERT™ – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS

THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

D Q

Output Routing Pool

D Q

Logic

Array

D Q

GLB

D Q

Global Routing Pool (GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Description

The ispLSI and pLSI 1032E are High Density Program-

mable Logic Devices containing 192 Registers, 64

Universal I/O pins, eight Dedicated Input pins, four Dedi-

cated Clock Input pins and a Global Routing Pool (GRP).

The GRP provides complete interconnectivity between

all of these elements. The ispLSI 1032E features 5-Volt

in-system programmability and in-system diagnostic ca-

pabilities. The ispLSI 1032E device offers non-volatile

reprogrammability of the logic, as well as the intercon-

nects to provide truly reconfigurable systems. It is

architecturally and parametrically compatible to the pLSI

1032E device, but multiplexes four input pins to control

in-system programming. A functional superset of the

ispLSI and pLSI 1032 architecture, the ispLSI and pLSI

1032E devices add two new global output enable pins.

The basic unit of logic on the ispLSI and pLSI 1032E

devices is the Generic Logic Block (GLB). The GLBs are

labeled A0, A1…D7 (see Figure 1). There are a total of 32

GLBs in the ispLSI and pLSI 1032E devices. Each GLB

has 18 inputs, a programmable AND/OR/Exclusive OR

array, and four outputs which can be configured to be

either combinatorial or registered. Inputs to the GLB

come from the GRP and dedicated inputs. All of the GLB

outputs are brought back into the GRP so that they can

be connected to the inputs of any GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

October 1998

1032E_06

Output Routing Pool

0139A(A1)-isp

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