CY14B104NA
4-Mbit (256K × 16) Automotive nvSRAM
4-Mbit (256K × 16) Automotive nvSRAM
Features
■
■
■
■
■
■
■
■
25 ns and 45 ns access times
Internally organized as 256K × 16
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
❐
Infinite read, write, and recall cycles
❐
STORE cycles to QuantumTrap
• Automotive-A: 1,000K STORE cycles
• Automotive-E: 100K STORE cycles
Data retention
❐
Automotive-A: 20 years
❐
Automotive-E: 1 year
Automotive-A Temperature: –40
C
to +85
C
❐
Single 3 V +20, -10 Operation
Automotive-E Temperature: –40
C
to +125
C
❐
Single 3.3 V + 0.3 V Operation
Packages
❐
48-ball fine-pitch ball grid array (FBGA)
❐
44-pin thin small outline package (TSOP) Type II
Pb-free and restriction of hazardous substances (RoHS)
compliant
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Functional Description
The Cypress CY14B104NA is a fast static RAM (SRAM), with a
non-volatile element in each memory cell. The memory is
organized as 256K words of 16-bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
non-volatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
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Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-54469 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY14B104NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
SRAM Read ................................................................ 5
SRAM Write ................................................................. 5
AutoStore Operation .................................................... 5
Hardware STORE Operation ....................................... 5
Hardware RECALL (Power-Up) .................................. 6
Software STORE ......................................................... 6
Software RECALL ....................................................... 6
Preventing AutoStore .................................................. 8
Data Protection ............................................................ 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads ................................................................ 11
AC Test Conditions ........................................................ 11
AC Switching Characteristics ....................................... 12
Switching Waveforms .................................................... 13
AutoStore/Power-Up RECALL ....................................... 16
Switching Waveforms
– AutoStore/Power-up RECALL .................................... 16
Software Controlled STORE/RECALL Cycle ................ 17
Switching Waveforms
– Software Controlled STORE/RECALL Cycle ............. 17
Hardware STORE Cycle ................................................. 18
Switching Waveforms – Hardware STORE Cycle ........ 18
Truth Table For SRAM Operations ................................ 19
Ordering Information ...................................................... 20
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 001-54469 Rev. *I
Page 2 of 25
CY14B104NA
Pinouts
Figure 1. 48-ball FBGA pinout
48-ball FBGA
(× 16)
Top View
(not to scale)
1
BLE
DQ
8
2
OE
BHE
3
A
0
A
3
A
5
A
17
V
CAP
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
DQ
1
DQ
3
DQ
4
DQ
5
WE
A
11
6
NC
DQ
0
DQ
2
V
CC
V
SS
DQ
6
DQ
7
NC
A
B
C
D
E
F
G
H
DQ
9
DQ
10
V
SS
DQ
11
V
CC
DQ
12
DQ
14
DQ
13
DQ
15
HSB
NC
[1]
A
8
Figure 2. 44-pin TSOP II pinout
(× 16)
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
[3]
44-pin TSOP II
(× 16)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
Notes
1. Address expansion for 8-Mbit. NC pin not connected to die.
2. Address expansion for 16-Mbit. NC pin not connected to die.
3. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document Number: 001-54469 Rev. *I
Page 3 of 25
CY14B104NA
Pin Definitions
Pin Name
A
0
–A
17
WE
CE
OE
BHE
BLE
V
SS
V
CC
HSB
I/O Type
Input
Input
Input
Input
Input
Input
Ground
Description
Address inputs.
Used to Select one of the 262,144 words of the nvSRAM.
Write Enable input, Active LOW.
When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Byte High Enable, Active LOW.
Controls DQ
15
–DQ
8
.
Byte Low Enable, Active LOW.
Controls DQ
7
–DQ
0
.
Ground for the device.
Must be connected to the ground of the system.
DQ
0
–DQ
15
Input/Output
Bidirectional data I/O lines.
Used as input or output lines depending on operation.
Power supply
Power supply inputs to the device.
Input/Output
Hardware STORE Busy (HSB).
When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (t
HHHD
) with standard output high
current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No connect
No Connect.
This pin is not connected to the die.
V
CAP
NC
Document Number: 001-54469 Rev. *I
Page 4 of 25
CY14B104NA
Device Operation
The CY14B104NA nvSRAM is made up of two functional
components paired in the same physical cell. They are a SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104NA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the non-volatile cells. Refer to the
Truth Table For SRAM
Operations on page 19
for a complete description of read and
write modes.
AutoStore on page 8.
In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 3
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics on page 9
for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
V
CC
SRAM Read
The CY14B104NA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A
0–17
determines which of the 262,144 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of t
AA
(read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at t
ACE
or at t
DOE
, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the t
AA
access time without the need for transi-
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
0.1 uF
10 kOhm
V
CC
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–15
are written into the memory if the data is valid (t
SD
time) before
the end of a WE controlled write or before the end of an CE
controlled write. The Byte Enable inputs (BHE, BLE) determine
which bytes are written, in the case of 16-bit words. It is recom-
mended that OE be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
WE
V
CAP
V
CAP
V
SS
Hardware STORE Operation
The CY14B104NA provides the HSB pin to control and
acknowledge the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104NA conditionally initiates a STORE
operation after t
DELAY
. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
DELAY
) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104NA. But any SRAM read and write cycles
AutoStore Operation
The CY14B104NA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by the HSB; Software STORE activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104NA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
Document Number: 001-54469 Rev. *I
Page 5 of 25
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