DATASHEET
EL7158
Ultra-High Current Pin Driver
The EL7158 high performance pin driver with three-state is
suited to many ATE and level-shifting applications. The 12A
peak drive capability makes this part an excellent choice
when driving high capacitance loads.
The output pin OUT is connected to input pins VH or VL
respectively, depending on the status of the IN pin. When the
OE pin is active low, the output is placed in the three-state
mode. The isolation of the output FETs from the power
supplies enables VH and VL to be set independently,
enabling level-shifting to be implemented. Related to the
EL7155, the EL7158 adds a lower supply pin VS- and makes
VL an isolated and independent input. This feature adds
applications flexibility and improves switching response due
to the increased enhancement of the output FETs.
This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and ON-resistance characteristics.
Available in the 8 Ld SOIC package, the EL7158 is specified
for operation over the full -40°C to +85°C temperature range.
FN7349
Rev 2.00
May 14, 2007
Features
• Clocking speeds up to 40MHz
• 12ns t
R
/t
F
at 2000pF C
LOAD
• 0.2ns rise and fall times mismatch
• 0.5ns t
ON
-t
OFF
prop delay mismatch
• 3.5pF typical input capacitance
• 12A peak drive
• Low ON-resistance of 0.5
• High capacitive drive capability
• Operates from 4.5V to 12V
• Pb-free plus anneal available (RoHS compliant)
Applications
• ATE/burn-in testers
• Level shifting
• IGBT drivers
• CCD drivers
Pinout
EL7158
(8 LD SOIC)
TOP VIEW
VS+ 1
OE 2
IN 3
GND 4
L
O
G
I
C
8 VH
7 OUT
6 VL
5 VS-
Ordering Information
PART
NUMBER
EL7158IS
EL7158IS-T7
EL7158IS-T13
EL7158ISZ
(Note)
EL7158ISZ-T7
(Note)
PART
MARKING
7158IS
7158IS
7158IS
7158ISZ
7158ISZ
PACKAGE
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
TAPE &
REEL
-
7”
13”
-
7”
13”
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
EL7158ISZ-T13 7158ISZ
(Note)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
FN7349 Rev 2.00
May 14, 2007
Page 1 of 9
EL7158
Absolute Maximum Ratings
(T
A
= +25°C)
Supply Voltage (V
S
+ to V
S
-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
- -0.3V, V
S
+0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
INPUT
V
IH
I
IH
V
IL
I
IL
C
IN
R
IN
OUTPUT
R
OVH
R
OVL
I
OUT
I
PK
V
S
+ = +12V, V
H
= +12V, V
L
= 0V, V
S
- = 0V, T
A
= +25°C, unless otherwise specified.
CONDITION
MIN
TYP
MAX
UNIT
DESCRIPTION
Logic ‘1’ Input Voltage
Logic ‘1’ Input Current
Logic ‘0’ Input Voltage
Logic ‘0’ Input Current
Input Capacitance
Input Resistance
V
IL
= 0V
V
IH
= V
S
+
2.4
0.1
10
0.8
0.1
3.5
50
10
V
µA
V
µA
pF
M
ON-Resistance V
H
to OUT
ON-Resistance V
L
to OUT
Output Leakage Current
Peak Output Current
(linear resistive operation)
Continuous Output Current
I
OUT
= -500mA
I
OUT
= +500mA
OE = 0V, OUT = V
H
/V
L
Source
Sink
Source/Sink
500
0.5
0.5
0.1
12
12
1
1
10
µA
A
A
mA
I
DC
POWER SUPPLY
I
S
I
VH
Power Supply Current
Off Leakage at V
H
and V
L
Inputs = V
S
+
V
H
, V
L
= 0V
1.3
4
3
10
mA
µA
SWITCHING CHARACTERISTICS
t
R
t
F
t
RF
t
d-1
t
d-2
t
d
t
d-3
t
d-4
SR+
SR-
Rise Time
Fall Time
t
R
, t
F
Mismatch
Turn-Off Delay Time
Turn-On Delay Time
t
d-1
-t
d-2
Mismatch
Three-State Delay Enable
Three-State Delay Disable
V
OUT
+ Slew Rate
V
OUT
- Slew Rate
R
LOAD
= 6
R
LOAD
= 6
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
12.0
12.2
0.2
22.5
22.0
0.5
22
22
800
800
ns
ns
ns
ns
ns
ns
ns
ns
V/µs
V/µs
FN7349 Rev 2.00
May 14, 2007
Page 2 of 9
EL7158
Electrical Specifications
PARAMETER
INPUT
V
IH
I
IH
V
IL
I
IL
C
IN
R
IN
OUTPUT
R
OVH
R
OVL
I
OUT
I
PK
ON-Resistance V
H
to OUT
ON-Resistance V
L
to OUT
Output Leakage Current
Peak Output Current
(linear resistive operation)
Continuous Output Current
I
OUT
= -500mA
I
OUT
= +500mA
OE = 0V, OUT = V
H
/V
L
Source
Sink
Source/Sink
500
0.5
0.5
0.1
1.2
1.2
1
1
10
µA
A
A
mA
Logic ‘1’ Input Voltage
Logic ‘1’ Input Current
Logic ‘0’ Input Voltage
Logic ‘0’ Input Current
Input Capacitance
Input Resistance
V
IL
= 0V
0.1
3.5
50
V
IH
= V
S
+
2.0
0.1
10
0.8
10
V
µA
V
µA
pF
M
V
S
+ = +12V, V
H
= +1.2V, V
L
= 0V, V
S
- = 0V, T
A
= +25°C, unless otherwise specified. (Continued)
CONDITION
MIN
TYP
MAX
UNIT
DESCRIPTION
I
DC
POWER SUPPLY
I
S
V
H
Power Supply Current
Off Leakage at V
H
and V
L
Inputs = V
S
+
V
H
, V
L
= 0V
1
4
2.5
10
mA
µA
SWITCHING CHARACTERISTICS
t
R
t
F
t
RF
t
d-1
t
d-2
t
d
t
d-3
t
d-4
SR+
SR-
Rise Time
Fall Time
t
R
, t
F
Mismatch
Turn-Off Delay Time
Turn-On Delay Time
t
d-1
-t
d-2
Mismatch
Three-State Delay Enable
Three-State Delay Disable
V
OUT
+ Slew Rate
V
OUT
- Slew Rate
R
LOAD
= 6
R
LOAD
= 6
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
C
L
= 2000pF
11
11
0
20.5
20.0
0.5
20
20
80
80
ns
ns
ns
ns
ns
ns
ns
ns
V/µs
V/µs
FN7349 Rev 2.00
May 14, 2007
Page 3 of 9
EL7158
Typical Performance Curves
1.8
T = +25°C
2.0
HIGH THRESHOLD
INPUT VOLTAGE (V)
1.6
HYSTERESIS
SUPPLY CURRENT (mA)
1.6
1.2
0.8
0.4
0
5
10
SUPPLY VOLTAGE (V)
12
5
10
SUPPLY VOLTAGE (V)
12
T = +25°C
1.4
ALL INPUTS = GND
1.2
LOW THRESHOLD
ALL INPUTS = V
S
+
1.0
FIGURE 1. INPUT THRESHOLD vs SUPPLY VOLTAGE
FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
I
OUT
= 500mA, T = +25°C, V
S
+ = V
H
, V
S
- = V
L
= 0V
0.8
“ON” RESISTANCE ()
15
C
L
= 2000pF, T = +25°C, V
S
+ = V
H
, V
S
- = V
L
= 0V
0.7
V
H
TO V
OUT
RISE/FALL TIME (ns)
14
t
R
13
0.6
0.5
V
OUT
TO V
L
12
t
F
0.4
5
7.5
10
12.5
11
5
6
7
8
9
10
11
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 3. “ON”-RESISTANCE vs SUPPLY VOLTAGE (V
S
+)
FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE
18
16
14
12
10
C
L
= 2000pF, V
S
+ = V
H
= 12V, V
S
- = V
L
= 0V
30
28
DELAY TIME (ns)
C
L
= 2000pF, T = +25°C, V
S
+ = V
H
= 12V,
V
S
- = V
L
= 0V
RISE/FALL TIME (ns)
t
R
t
r
26
24
22
20
t
d2
t
d1
t
R
8
-50
0
50
TEMPERATURE (°C)
100
150
5
6
7
8
9
10
11
12
SUPPLY VOLTAGE (V)
FIGURE 5. RISE/FALL TIME vs TEMPERATURE
FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE
FN7349 Rev 2.00
May 14, 2007
Page 4 of 9
EL7158
Typical Performance Curves
(Continued)
26
C
L
= 2000pF, V
S
+ = V
H
= 12V, V
S
- = V
L
= 0V
70
60
V
S
+ = +12V, T = +25°C
DELAY TIME (ns)
t
D1
RISE/FALL TIME (ns)
24
50
40
t
F
30
20
10
t
R
22
t
D2
20
18
-50
-25
0
25
50
75
100
125
0
100
1k
LOAD CAPACITANCE (pF)
10k
TEMPERATURE (°C)
FIGURE 7. PROPAGATION DELAY vs TEMPERATURE
FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE
5
4
3
2
1
V
S
+ = V
H
= 12V, V
S
- = V
L
= 0V, T = +25°C, f = 20kHz
100
C
L
= 1000pF, T = +25°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10
V
S
+=12V
1.0
V
S
+=5V
0.1
10k
100k
1M
V
S
+=10V
0
100
1k
LOAD CAPACITANCE (pF)
10k
10M
FREQUENCY (Hz)
FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE
FIGURE 10. SUPPLY CURRENT vs FREQUENCY
1.0
0.9
POWER DISSIPATION (W)
0.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
POWER DISSIPATION (W)
1.2
1.0
0.8
0.6
0.4
0.2
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.7 625mW
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
JA
=
909mW
JA
SO
I
16
0
C8
/W
=
°C
11
SO
I
C8
0°
C/
W
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7349 Rev 2.00
May 14, 2007
Page 5 of 9
京公网安备 11010802033920号
EEWORLD
