MX30LF2G28AB-TI datasheet, PDF

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MX30LF2G28AB-TI: DescriptionIC FLASH 2G PARALLEL 48TSOP; Categorystorage storage; File Size1007KB，78 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx; Environmental Compliance

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MX30LF2G28AB-TI Overview

IC FLASH 2G PARALLEL 48TSOP

MX30LF2G28AB-TI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Macronix
package instruction	TSOP1,
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Factory Lead Time	16 weeks
JESD-30 code	R-PDSO-G48
length	18.4 mm
memory density	2147483648 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	48
word count	268435456 words
character code	256000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	2.7 V
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
type	SLC NAND TYPE
width	12 mm

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MX30LF2G28AB

MX30LF4G28AB

3V, 2G/4G-bit NAND Flash Memory

MX30LFxG28AB

P/N: PM2029

REV. 1.3, February 08, 2017

MX30LF2G28AB

MX30LF4G28AB

Contents

1. FEATURES........................................................................................................................................6

2. GENERAL DESCRIPTIONS .............................................................................................................7

Figure 1. Logic Diagram ......................................................................................................................... 7

2-1.

3-1.

ORDERING INFORMATION ...................................................................................................8

PIN DESCRIPTIONS .............................................................................................................12

3. PIN CONFIGURATIONS .................................................................................................................10

4. BLOCK DIAGRAM ..........................................................................................................................14

5. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT ......................................................15

Table 1-1. Address Allocation ............................................................................................................... 15

6. DEVICE OPERATIONS ...................................................................................................................16

6-1.

Address Input/Command Input/Data Input........................................................................16

Figure 2. AC Waveforms for Command / Address / Data Latch Timing ............................................... 16

Figure 3. AC Waveforms for Address Input Cycle ................................................................................ 16

Figure 4. AC Waveforms for Command Input Cycle ............................................................................ 17

Figure 5. AC Waveforms for Data Input Cycle ..................................................................................... 17

Figure 6. AC Waveforms for Read Cycle ............................................................................................. 18

Figure 7. AC Waveforms for Read Operation (Intercepted by CE#) .................................................... 19

Figure 8. AC Waveforms for Read Operation (with CE# Don't Care)................................................... 20

Figure 9-1. AC Waveforms for Sequential Data Out Cycle (After Read) .............................................. 20

Figure 9-2. AC Waveforms for Sequential Data Out Cycle (After Read) - EDO Mode ......................... 21

Figure 10. AC Waveforms for Random Data Output ............................................................................ 22

Figure 11-1. AC Waveforms for Cache Read Sequential ..................................................................... 24

Figure 11-2. AC Waveforms for Cache Read Random ........................................................................ 26

6-2.

Page Read ............................................................................................................................18

6-3.

6-4.

6-5.

Cache Read Sequential .......................................................................................................23

Cache Read Random ...........................................................................................................25

Page Program ......................................................................................................................27

Figure 12. AC Waveforms for Program Operation after Command 80H .............................................. 27

Figure 13. AC Waveforms for Random Data In (For Page Program) ................................................... 28

Figure 14. AC Waveforms for Program Operation with CE# Don't Care .............................................. 29

P/N: PM2029

REV. 1.3, February 08, 2017

MX30LF2G28AB

MX30LF4G28AB

6-6.

Cache Program ....................................................................................................................30

Figure 15-1. AC Waveforms for Cache Program ................................................................................. 31

Figure 15-2. AC Waveforms for Sequence of Cache Program ........................................................... 32

Figure 16. AC Waveforms for Erase Operation .................................................................................... 33

6-7.

6-8.

Block Erase ..........................................................................................................................33

ID Read .................................................................................................................................34

Table 2. ID Codes Read Out by ID Read Command 90H .................................................................... 34

Table 3. The Definition of Byte2~Byte4 of ID Table

.............................................................................. 35

Figure 17-1. AC Waveforms for ID Read Operation ............................................................................. 36

Figure 17-2. AC Waveforms for ID Read (ONFI Identifier) Operation

.................................................. 36

6-9.

Status Read ..........................................................................................................................37

Table 4. Status Output.......................................................................................................................... 37

Figure 18. Bit Assignment (HEX Data)

................................................................................................. 38

Figure 19. AC Waveforms for Status Read Operation ......................................................................... 38

6-10. Status Enhance Read ..........................................................................................................39

6-11. Reset .....................................................................................................................................40

6-12. Parameter Page Read (ONFI) ..............................................................................................41

Figure 20. AC Waveforms for Status Enhance Operation .................................................................... 39

Figure 21. AC waveforms for Reset Operation .................................................................................... 40

Figure 22. AC waveforms for Parameter Page Read (ONFI) Operation ............................................. 41

Figure 23. AC Waveforms for Parameter Page Read (ONFI) Random Operation (For 05h-E0h) ....... 42

Table 5. Parameter Page (ONFI) ......................................................................................................... 43

Figure 24. AC waveforms for Unique ID Read Operation .................................................................... 46

Figure 25. AC waveforms for Unique ID Read Operation (For 05h-E0h) ............................................. 47

Table 6-1. Definition of Feature Address

.............................................................................................. 48

Table 6-2. Sub-Feature Parameter Table of Feature Address - 90h (Array Operation Mode).............. 48

6-14-1. Set Feature (ONFI) ................................................................................................................. 49

Figure 26. AC Waveforms for Set Feature (ONFI) Operation ............................................................. 49

6-14-2. Get Feature (ONFI) ................................................................................................................. 50

Figure 27. AC Waveforms for Get Feature (ONFI) Operation .............................................................. 50

6-14-3. Secure OTP (One-Time-Programmable) Feature ................................................................ 51

Figure 28. AC Waveforms for OTP Data Read .................................................................................... 51

Figure 29. AC Waveforms for OTP Data Read with Random Data Output .......................................... 52

Figure 30. AC Waveforms for OTP Data Program ............................................................................... 53

Figure 31. AC Waveforms for OTP Data Program with Random Data Input........................................ 54

Figure 32. AC Waveforms for OTP Protection Operation .................................................................... 55

6-13. Unique ID Read (ONFI) ........................................................................................................45

6-14. Feature Set Operation (ONFI) .............................................................................................48

P/N: PM2029

REV. 1.3, February 08, 2017

MX30LF2G28AB

MX30LF4G28AB

6-15. Two-Plane Operations .........................................................................................................56

6-16. Two-plane Program (ONFI) and Two-plane Cache Program (ONFI) ................................56

Figure 33-1. AC Waveforms for Two-plane Program (ONFI) ............................................................... 57

Figure 33-2. AC Waveforms for Page Program Random Data Two-plane (ONFI) ............................... 58

Figure 34. AC Waveforms for Two-plane Cache Program (ONFI) ....................................................... 59

Figure 35. AC Waveforms for Two-plane Erase (ONFI) ....................................................................... 60

6-17. Two-plane Block Erase (ONFI) ............................................................................................60

7. PARAMETERS ................................................................................................................................61

7-1.

ABSOLUTE MAXIMUM RATINGS........................................................................................61

Figure 36. Maximum Negative Overshoot............................................................................................ 61

Figure 37. Maximum Positive Overshoot ............................................................................................. 61

Table 7. Operating Range .................................................................................................................... 62

Table 8. DC Characteristics.................................................................................................................. 62

Table 9. Capacitance............................................................................................................................ 63

Table 10. AC Testing Conditions .......................................................................................................... 63

Table 11. Program and Erase Characteristics ...................................................................................... 63

Table 12. AC Characteristics ................................................................................................................ 64

8. OPERATION MODES: LOGIC AND COMMAND TABLES ............................................................65

Table 13. Logic Table ........................................................................................................................... 65

Table 14-1. HEX Command Table

........................................................................................................ 66

Table 14-2. Two-plane Command Set .................................................................................................. 66

8-1.

8-2.

R/B#: Termination for The Ready/Busy# Pin (R/B#) ........................................................67

Power On/Off Sequence ......................................................................................................69

Figure 38. R/B# Pin Timing Information

............................................................................................... 68

Figure 39. Power On/Off Sequence .................................................................................................... 69

8-2-1. WP# Signal ............................................................................................................................. 70

Figure 40-1. Enable Programming of WP# Signal ............................................................................... 70

Figure 40-2. Disable Programming of WP# Signal .................................................................................. 70

Figure 40-3. Enable Erasing of WP# Signal ......................................................................................... 70

Figure 40-4. Disable Erasing of WP# Signal ........................................................................................ 70

9. SOFTWARE ALGORITHM..............................................................................................................71

9-1.

Invalid Blocks (Bad Blocks) ...............................................................................................71

Figure 41. Bad Blocks

.......................................................................................................................... 71

Table 15. Valid Blocks

.......................................................................................................................... 71

Figure 42. Bad Block Test Flow

............................................................................................................ 72

9-2.

Bad Block Test Flow ............................................................................................................72

P/N: PM2029

REV. 1.3, February 08, 2017

MX30LF2G28AB-TI Related Products

	MX30LF2G28AB-TI	MX30LF4G28AB-TI	MX30LF4G28AB-XKI	MX30LF2G28AB-XKI
Description	IC FLASH 2G PARALLEL 48TSOP	IC FLASH 4G PARALLEL 48TSOP	IC FLASH 4G PARALLEL 63VFBGA	IC FLASH 2G PARALLEL 63VFBGA
technology	CMOS	FLASH - NAND （SLC）	FLASH - NAND （SLC）	CMOS

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