C8051F96x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power Consumption at 3.6 V
-
130 µA/MHz Low-Power Active mode with dc-dc
enabled
-
120 nA sleep current w/ data retention; POR monitor
enabled
-
450 nA sleep mode with SmaRTClock
(internal LFO)
-
600 nA sleep mode with SmaRTClock (ext. crystal)
-
2 µs wakeup time; 1.5 µA analog settling time
12-Bit; 16 Ch. Analog-to-Digital Converter
-
Up to 75 ksps (12-bit mode) or 300 ksps
(10-bit mode)
-
External pin or internal VREF (no ext cap required)
-
On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
-
Autonomous burst mode with 16-bit auto-averaging
accumulator
-
Integrated temperature sensor
Two Low Current Comparators
-
Programmable hysteresis and response time
-
Configurable as wake-up or reset source
Internal 6-Bit Current Reference
-
Up to ±500 µA; source and sink capability
-
Enhanced resolution via PWM interpolation
Integrated LCD Controller
-
Supports up to 128 segments (32x4)
-
LCD controller consumes only 400 nA for
32-segment static display
-
Integrated charge pump for contrast control
Metering-Specific Peripherals
-
DC-DC buck converter allows dynamic voltage
scaling for maximum efficiency (250 mW output)
-
Sleep-mode pulse accumulator with programmable
switch, de-bounce and pull-up control; interfaces
directly to metering sensor
-
Data Packet Processing Engine (DPPE) includes
hardware AES, DMA, CRC and encoding blocks for
acceleration of wireless protocols
Power On
Reset/PMU
Wake
Reset
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Memory
-
Up to 128 kB Flash; In-system programmable; Full
read/write/erase functionality over supply range
-
Up to 8 kB internal data RAM
Digital Peripherals
-
57 or 34 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
-
Hardware SMBus™ (I
2
C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
-
Four general purpose 16-bit counter/timers
-
Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
-
Precision Internal oscillator: 24.5 MHz, 2% accuracy
supports UART operation; spread-spectrum mode
for reduced EMI
-
Low power internal oscillator: 20 MHz
-
External oscillator: Crystal, RC, C, or CMOS Clock
-
SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz
internal LFO
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
-
Provides 4 breakpoints, single stepping
Packages
-
76-pin DQFN (6 x 6 mm)
-
40-pin QFN (6 x 6 mm)
-
80-pin TQFP (12 x 12 mm)
Temperature Range: –40 to +85 °C
CIP-51 8051
Controller Core
128k Byte ISP Flash
Program Memory
256 Byte SRAM
8092 Byte XRAM
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1, 2, 3
PCA/WDT
SMBus
Priority
Crossbar
Decoder
Port 0
Drivers
C2CK/RST
Debug /
Programming
Hardware
C2D
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5/INT5
P1.6/INT6
P1.7
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
P2.5
P2.6
P2.7
32
DMA
VBAT
VDC
VBAT
VDD
Analog
Power
SPI 0
SPI 1
(DMA Enabled)
CRC
Engine
AES
Engine
Encoder
VREG
Digital
Power
Port 1
Drivers
Crossbar Control
VBATDC
IND
GNDDC
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
LCD Charge
Pump
XTAL1
XTAL2
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
SYSCLK
SFR
Bus
LCD (up to 4x32)
EMIF
Pulse Counter
Port 2
Drivers
Analog Peripherals
Internal
VREF
External
VREF
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
CP1, CP1A
+
-
CAP
P3-6
Drivers
P7
Driver
P3.0...P6.7
16
GND
XTAL3
XTAL4
12-bit
75ksps
ADC
P7.0/C2D
System Clock
Configuration
+
-
Comparators
Rev. 1.0 7/13
Copyright © 2013 by Silicon Laboratories
C8051F96x
C8051F96x
Table of Contents
1. System Overview ..................................................................................................... 22
1.1. CIP-51™ Microcontroller Core .......................................................................... 28
1.1.1. Fully 8051 Compatible .............................................................................. 28
1.1.2. Improved Throughput................................................................................ 28
1.1.3. Additional Features ................................................................................... 28
1.2. Port Input/Output ............................................................................................... 29
1.3. Serial Ports ........................................................................................................ 30
1.4. Programmable Counter Array............................................................................ 30
1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode ..................................................................................... 31
1.6. Programmable Current Reference (IREF0)....................................................... 32
1.7. Comparators...................................................................................................... 32
2. Ordering Information ............................................................................................... 34
3. Pinout and Package Definitions ............................................................................. 35
3.1. DQFN-76 Package Specifications ..................................................................... 46
3.1.1. Package Drawing ...................................................................................... 46
3.1.2. Land Pattern.............................................................................................. 47
3.1.3. Soldering Guidelines ................................................................................. 48
3.2. QFN-40 Package Specifications........................................................................ 50
3.3. TQFP-80 Package Specifications...................................................................... 52
3.3.1. Soldering Guidelines ................................................................................. 55
4. Electrical Characteristics ........................................................................................ 56
4.1. Absolute Maximum Specifications..................................................................... 56
4.2. Electrical Characteristics ................................................................................... 57
5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode........................................................................................... 78
5.1. Output Code Formatting .................................................................................... 78
5.2. Modes of Operation ........................................................................................... 80
5.2.1. Starting a Conversion................................................................................ 80
5.2.2. Tracking Modes......................................................................................... 80
5.2.3. Burst Mode................................................................................................ 82
5.2.4. Settling Time Requirements...................................................................... 83
5.2.5. Gain Setting .............................................................................................. 83
5.3. 8-Bit Mode ......................................................................................................... 84
5.4. 12-Bit Mode ....................................................................................................... 84
5.5. Low Power Mode............................................................................................... 85
5.6. Programmable Window Detector....................................................................... 91
5.6.1. Window Detector In Single-Ended Mode .................................................. 93
5.6.2. ADC0 Specifications ................................................................................. 94
5.7. ADC0 Analog Multiplexer .................................................................................. 95
5.8. Temperature Sensor.......................................................................................... 97
5.8.1. Calibration ................................................................................................. 97
5.9. Voltage and Ground Reference Options ......................................................... 100
Rev. 1.0
2
C8051F96x
5.10. External Voltage Reference........................................................................... 101
5.11. Internal Voltage Reference............................................................................ 101
5.12. Analog Ground Reference............................................................................. 101
5.13. Temperature Sensor Enable ......................................................................... 101
5.14. Voltage Reference Electrical Specifications .................................................. 102
6. Programmable Current Reference (IREF0).......................................................... 103
6.1. PWM Enhanced Mode..................................................................................... 103
6.2. IREF0 Specifications ....................................................................................... 104
7. Comparators........................................................................................................... 105
7.1. Comparator Inputs........................................................................................... 105
7.2. Comparator Outputs ........................................................................................ 106
7.3. Comparator Response Time ........................................................................... 107
7.4. Comparator Hysterisis ..................................................................................... 107
7.5. Comparator Register Descriptions .................................................................. 108
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112
8. CIP-51 Microcontroller........................................................................................... 115
8.1. Instruction Set.................................................................................................. 116
8.1.1. Instruction and CPU Timing .................................................................... 116
8.2. CIP-51 Register Descriptions .......................................................................... 121
9. Memory Organization ............................................................................................ 124
9.1. Program Memory............................................................................................. 124
9.1.1. MOVX Instruction and Program Memory ................................................ 127
9.2. Data Memory ................................................................................................... 127
9.2.1. Internal RAM ........................................................................................... 127
9.2.2. External RAM .......................................................................................... 128
10. External Data Memory Interface and On-Chip XRAM ....................................... 129
10.1. Accessing XRAM........................................................................................... 129
10.1.1. 16-Bit MOVX Example .......................................................................... 129
10.1.2. 8-Bit MOVX Example ............................................................................ 129
10.2. Configuring the External Memory Interface ................................................... 130
10.3. Port Configuration.......................................................................................... 130
10.4. Multiplexed and Non-multiplexed Selection................................................... 134
10.4.1. Multiplexed Configuration...................................................................... 134
10.4.2. Non-multiplexed Configuration.............................................................. 134
10.5. Memory Mode Selection................................................................................ 135
10.5.1. Internal XRAM Only .............................................................................. 136
10.5.2. Split Mode without Bank Select............................................................. 136
10.5.3. Split Mode with Bank Select.................................................................. 136
10.5.4. External Only......................................................................................... 136
10.6. Timing .......................................................................................................... 137
10.6.1. Non-Multiplexed Mode .......................................................................... 139
10.6.2. Multiplexed Mode .................................................................................. 142
11. Direct Memory Access (DMA0)........................................................................... 146
11.1. DMA0 Architecture ........................................................................................ 147
11.2. DMA0 Arbitration ........................................................................................... 148
3
Rev. 1.0
C8051F96x
11.2.1. DMA0 Memory Access Arbitration ........................................................ 148
11.2.2. DMA0 Channel Arbitration .................................................................... 148
11.3. DMA0 Operation in Low Power Modes ......................................................... 148
11.4. Transfer Configuration................................................................................... 149
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 160
12.1. 16-bit CRC Algorithm..................................................................................... 160
12.3. Preparing for a CRC Calculation ................................................................... 163
12.4. Performing a CRC Calculation ...................................................................... 163
12.5. Accessing the CRC0 Result .......................................................................... 163
12.6. CRC0 Bit Reverse Feature............................................................................ 167
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 168
13.1. Polynomial Specification................................................................................ 168
13.2. Endianness.................................................................................................... 169
13.3. CRC Seed Value ........................................................................................... 170
13.4. Inverting the Final Value................................................................................ 170
13.5. Flipping the Final Value ................................................................................. 170
13.6. Using CRC1 with SFR Access ...................................................................... 171
13.7. Using the CRC1 module with the DMA ......................................................... 171
14. Advanced Encryption Standard (AES) Peripheral ............................................ 175
14.1. Hardware Description .................................................................................... 176
14.1.1. AES Encryption/Decryption Core .......................................................... 177
14.1.2. Data SFRs............................................................................................. 177
14.1.3. Configuration sfrs .................................................................................. 178
14.1.4. Input Multiplexer.................................................................................... 178
14.1.5. Output Multiplexer ................................................................................. 178
14.1.6. Internal State Machine .......................................................................... 178
14.2. Key Inversion................................................................................................. 179
14.2.1. Key Inversion using DMA...................................................................... 180
14.2.2. Key Inversion using SFRs..................................................................... 181
14.2.3. Extended Key Output Byte Order.......................................................... 182
14.2.4. Using the DMA to unwrap the extended Key ........................................ 183
14.3. AES Block Cipher .......................................................................................... 184
14.4. AES Block Cipher Data Flow......................................................................... 185
14.4.1. AES Block Cipher Encryption using DMA ............................................. 186
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 187
14.5. AES Block Cipher Decryption........................................................................ 188
14.5.1. AES Block Cipher Decryption using DMA............................................. 188
14.5.2. AES Block Cipher Decryption using SFRs............................................ 189
14.6. Block Cipher Modes ...................................................................................... 190
14.6.1. Cipher Block Chaining Mode................................................................. 190
14.6.2. CBC Encryption Initialization Vector Location....................................... 192
14.6.3. CBC Encryption using DMA .................................................................. 192
14.6.4. CBC Decryption .................................................................................... 195
14.6.5. Counter Mode ....................................................................................... 198
14.6.6. CTR Encryption using DMA .................................................................. 200
Rev. 1.0
4
Power technology
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