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COREFFT-UR

Description
HW/SW/OTHER
CategoryDevelopment board/suite/development tools   
File Size321KB,15 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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CoreFFT Fast Fourier Transform
Product Summary
Intended Use
Fast Fourier Transform (FFT) Function for Actel
FPGAs
Synthesis and Simulation Support
Actel Libero IDE
Synthesis: Synplicity,
®
Synopsys
®
(Design Compiler /
FPGA Compiler), Exemplar™
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Key Features
Forward and Inverse 32-, 64-, 128-, 256-, 512-,
1,024-, and 2,048-Point Complex FFT
Decimation–In-Time (DIT) Radix-2 Implementation
Optimized for Actel FPGAs
Selection of Unconditional or Conditional Block
Floating-Point Scaling
Embedded
Generator
RAM-Block-Based
Twiddle
Factor
Contents
General Description ................................................... 1
CoreFFT Device Requirements ................................... 3
Architecture ................................................................ 4
Buffering Scheme ....................................................... 5
FFT Computation ........................................................ 5
Finite Word Length Considerations .......................... 6
CoreFFT Generator Parameters ................................. 7
I/O Signal Description ................................................ 8
I/O Interface and Timing ............................................ 9
References ................................................................ 11
A Sample Configuration File ................................... 11
Ordering Information .............................................. 11
Appendix I: Fast Fourier Transform ......................... 12
List of Changes ......................................................... 14
Datasheet Categories ............................................... 14
8- to 16-Bit Configurable Input/Output Data and
Twiddle Coefficients Precision
Naturally Ordered Input and Output Data
Two’s-Complement Fixed-Point Arithmetic
Built-In Memory Buffers
CoreFFT Provides Register Transfer Level (RTL)
Code and a Behavioral Testbench
Targeted Devices
ProASIC
®
3/E
ProASIC
PLUS®
Axcelerator
®
RTAX-S
General Description
CoreFFT is an RTL generator that produces an Actel
FPGA–optimized FFT engine. The resulting module
computes 32-, 64-, 128-, 256-, 512-, 1,024-, or 2,048-point
complex forward or inverse decimation-in-time (DIT)
FFTs. The input and output data is represented as
bb-bit
words comprising
b-bit
real and imaginary parts
(bb =
b
+
b; b
= 8 to 16 bits). Both the real and imaginary
parts of the input and output data are two’s-
complement numbers. The FFT module contains all the
necessary memory buffers and butterfly and control
logic, as well as a twiddle factor generator. A dual input
buffer and a single output buffer support simultaneous
input of the new data samples with FFT computation and
result output. The module processes frames (bursts) of
data with a frame size equal to the transform size of N
words. The FFT computational process occurs in a
Core Deliverables
Full Version
CoreFFT RTL Generator; Generates User-
Defined FFT Model and Test Harness; Fully
Supported in Actel Libero
®
Integrated Design
Environment (IDE)
Supports FFT Engine and Test Harness
Generation with Limited Parameters; Fully
Supported in Actel Libero IDE
Evaluation Version
May 2007
© 2007 Actel Corporation
v 4 .0
1
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