Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range of 1.2 V to 3.6 V
•
CMOS low power consumption
•
MULTIBYTE flow-trough standard pin-out architecture
•
Low inductance multiple power and ground pins for
minimum noise and ground bounce
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
All data inputs have bushold
•
Complies with JEDEC standard JESD8-B/JESD36
•
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
•
Packaged in plastic fine-pitch ball grid array package.
DESCRIPTION
74LVCH32244A
The 74LVCH32244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 V or 5 V devices. In 3-state
operation, outputs can handle 5 V. These features allow
the use of these devices in a mixed 3.3 V and 5 V
environment.
The 74LVCH32244A is a 32-bit non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by eight output enable inputs (1OE to 8OE).
A HIGH on pin nOE causes the outputs to assume a
high-impedance OFF-state.
To ensure the high-impedance state during power up or
power down, pin nOE should be tied to V
CC
through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH32244A bushold data inputs eliminates the
need for external pull-up resistors to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
PARAMETER
propagation delay nAn to nYn
3-state output enable time nOE to nYn
3-state output disable time nOE to nYn
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
12
4.0
pF
pF
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
3.0
3.5
3.7
5.0
ns
ns
ns
pF
UNIT
2004 May 13
2
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