GTL2010
10-bit bidirectional low voltage translator
Rev. 06 — 3 March 2008
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V
CC
by
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other ten matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features
I
10-bit bidirectional low voltage translator
I
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V
buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
I
Provides bidirectional voltage translation with no direction pin
I
Low 6.5
Ω
ON-state resistance (R
on
) between input and output pins (Sn/Dn)
I
Supports hot insertion
I
No power supply required: will not latch up
I
5 V tolerant inputs
I
Low standby current
I
Flow-through pinout for ease of printed-circuit board trace routing
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Packages offered: TSSOP24, HVQFN24
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
3. Applications
I
Any application that requires bidirectional or unidirectional voltage level translation
from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V
I
The open-drain construction with no direction pin is ideal for bidirectional low voltage
(for example, 1.0 V, 1.2 V, 1.5 V or 1.8 V) processor I
2
C-bus port translation to the
normal 3.3 V and/or 5.0 V I
2
C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL
signal levels
4. Ordering information
Table 1.
Ordering information
Package
Name
GTL2010PW
GTL2010BS
TSSOP24
HVQFN24
Description
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT355-1
Type number
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4
×
4
×
0.85 mm
4.1 Ordering options
Table 2.
Ordering options
Topside mark
GTL2010
2010
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
GTL2010PW
GTL2010BS
5. Functional diagram
DREF
GREF
D1
D10
SREF
S1
S10
002aac059
Fig 1.
Functional diagram
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
2 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
6. Pinning information
6.1 Pinning
21 GREF
SREF
S1
S2
S3
S4
S5
S6
S7
2
3
4
5
6
7
8
9
23 DREF
22 D1
21 D2
20 D3
19 D4
18 D5
17 D6
16 D7
15 D8
14 D9
13 D10
002aac057
S2
S3
S4
S5
S6
S7
1
2
3
4
5
6
D10 10
D9 11
D8 12
7
8
9
19 D1
18 D2
17 D3
16 D4
15 D5
14 D6
13 D7
002aac058
GTL2010PW
24 S1
terminal 1
index area
GTL2010BS
S8 10
S9 11
S10 12
S8
S9
Transparent top view
Fig 2.
Pin configuration for TSSOP24
Fig 3.
Pin configuration for HVQFN24
6.2 Pin description
Table 3.
Symbol
GND
SREF
S1 to S10
D1 to D10
DREF
GREF
[1]
Pin description
Pin
TSSOP24
1
2
3, 4, 5, 6, 7, 8, 9,
10, 11, 12
HVQFN24
22
[1]
23
ground (0 V)
source of reference transistor
Description
24, 1, 2, 3, 4, 5, 6, Port S1 to Port S10
7, 8, 9
22, 21, 20, 19, 18, 19, 18, 17, 16, 15, Port D1 to Port D10
17, 16, 15, 14, 13 14, 13, 12, 11, 10
23
24
20
21
drain of reference transistor
gate of reference transistor
HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
GTL2010_6
S10
22 GND
GND
1
24 GREF
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
20 DREF
23 SREF
3 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
7. Functional description
Refer also to
Figure 1 “Functional diagram”.
7.1 Function selection
Table 4.
Function selection, HIGH-to-LOW translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
DREF
H
H
H
L
SREF
[2]
0V
V
T
V
T
0 V
−
V
T
Input Dn
X
H
L
X
Output Sn
X
V
T[3]
L
[4]
X
Transistor
off
on
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
V
T
is equal to the SREF voltage.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
Table 5.
Function selection, LOW-to-HIGH translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
DREF
H
H
H
L
SREF
[2]
0V
V
T
V
T
0 V
−
V
T
Input Sn
X
V
T
L
X
Output Dn
X
H
[3]
L
[4]
X
Transistor
off
nearly off
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
V
T
is equal to the SREF voltage.
Dn is pulled up to V
CC
through an external resistor.
Dn follows the Sn input LOW.
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
4 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V
CC
through a pull-up resistor (typically 200 kΩ). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V
CC
). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 kΩ resistor
to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V to (V
CC
−
1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to V
CC
.
1.8 V
1.5 V
1.2 V
1.0 V
GND
V
CORE
CPU I/O
S2
SREF
S1
5V
200 kΩ
totem pole or
open-drain I/O
GREF
DREF
D1
CHIPSET I/O
D2
V
CC
increase bit size
by using 10-bit GTL2010
or 22-bit GTL2000
V
CC
S3
S4
S5
Sn
D3
3.3 V
CHIPSET I/O
D4
D5
Dn
002aac060
Typical bidirectional voltage translation.
Fig 4.
Bidirectional translation to multiple higher voltage levels such as an I
2
C-bus
application
GTL2010_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
5 of 20
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