PCA9600
Dual bidirectional bus buffer
Rev. 6 — 25 September 2015
Product data sheet
1. General description
The PCA9600 is designed to isolate I
2
C-bus capacitance, allowing long buses to be
driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a
higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface
between a normal I
2
C-bus and a range of other higher capacitance or different voltage
bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side
is compatible with the Fast-mode Plus (Fm+) specifications.
The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface
making it suitable for interfacing with buses that have non I
2
C-bus-compliant logic levels
such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.
The separation of the bidirectional I
2
C-bus signals into unidirectional TX and RX signals
enables the SDA and SCL signals to be transmitted via balanced transmission lines
(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX
signals may be connected together to provide a normal bidirectional signal.
2. Features and benefits
Bidirectional data transfer of I
2
C-bus signals
Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side
TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive
buses
1 MHz operation on up to 20 meters of wire (see
AN10658)
Supply voltage range of 2.5 V to 15 V with I
2
C-bus logic levels on SX/SY side
independent of supply voltage
Splits I
2
C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths
Low power supply current
ESD protection exceeds 3500 V HBM per JESD22-A114 and 1400 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8 and TSSOP8 (MSOP8)
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
3. Applications
Interface between I
2
C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
Interface between I
2
C-bus and SMBus (350
A)
standard or Fm+ standard
Simple conversion of I
2
C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250
Interfaces with opto-couplers to provide opto-isolation between I
2
C-bus nodes up to
1 MHz
Long distance point-to-point or multipoint architectures
4. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9600
9600
Package
Name
SO8
TSSOP8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm
Version
SOT96-1
SOT505-1
Type number
PCA9600D
PCA9600DP
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9600D,118
Package
SO8
Packing method
Minimum
order quantity
Temperature
T
amb
=
40 C
to +85
C
Type number
PCA9600D
REEL 13" Q1/T1
2500
*STANDARD MARK
SMD
REEL 13" Q1/T1
2500
*STANDARD MARK
SMD
PCA9600DP
PCA9600DP,118
TSSOP8
T
amb
=
40 C
to +85
C
PCA9600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 25 September 2015
2 of 32
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
5. Block diagram
V
CC
(2.5 V to 15 V)
8
PCA9600
SX (SDA)
1
3
2
SY (SCL)
7
5
6
4
GND
002aac835
TX (TxD, SDA)
RX (RxD, SDA)
TY (TxD, SCL)
RY (RxD, SCL)
Fig 1.
Block diagram of PCA9600
6. Pinning information
6.1 Pinning
SX
RX
TX
GND
1
2
8
7
V
CC
SY
RY
TY
SX
RX
TX
GND
1
2
3
4
002aac837
8
7
V
CC
SY
RY
TY
PCA9600D
3
4
002aac836
6
5
PCA9600DP
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
(MSOP8)
6.2 Pin description
Table 3.
Symbol
SX
RX
TX
GND
TY
RY
SY
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
I
2
C-bus (SDA or SCL)
receive signal
transmit signal
negative supply voltage
transmit signal
receive signal
I
2
C-bus (SDA or SCL)
positive supply voltage
PCA9600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 25 September 2015
3 of 32
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
7. Functional description
Refer to
Figure 1 “Block diagram of PCA9600”.
The PCA9600 has two identical buffers allowing buffering of SDA and SCL I
2
C-bus
signals. Each buffer is made up of two logic signal paths, a forward path from the I
2
C-bus
interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the
buffered bus input, pins RX and RY to drive the I
2
C-bus interface. These paths:
•
sense the voltage state of I
2
C-bus pins SX (and SY) and transmit this state to pin TX
(and TY respectively), and
•
sense the state of pins RX and RY and pull the I
2
C-bus pin LOW whenever pin RX or
pin RY is LOW.
The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is
identical.
The I
2
C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based
systems.
The logic threshold voltage levels at SX on this I
2
C-bus are independent of the IC supply
voltage V
CC
. The maximum I
2
C-bus supply voltage is 15 V.
When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal
3 mA with a V
OL
of 0.74 V maximum. That guarantees compliance with the Fast-mode
I
2
C-bus specification for all I
2
C-bus voltages greater than 3 V, as well as compliance with
SMBus or other systems that use TTL switching levels.
SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of
typically 300
A
(maximum 1 mA at
40 C).
When selecting the pull-up for the bus at SX,
the sink capability of other connected drivers should be taken into account. Most TTL
devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the
requirement to ensure the 0.8 V TTL LOW.
For Fast-mode I
2
C-bus operation, the other connected I
2
C-bus parts may have the
minimum sink capability of 3 mA. SX sources typically 300
A
(maximum 1 mA at
40 C),
which forms part of the external driver loading. When selecting the pull-up it is necessary
to subtract the SX pin pull-up current, so, worst-case at
40 C,
the allowed pull-up can be
limited (by external drivers) to 2 mA.
When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher
specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA
at V
OL
= 1 V maximum. That 1 V complies with the bus LOW requirement (0.25V
bus
) of
any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a
drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at
V
OL
= 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is
(5.5 V
1 V) / 7 mA = 643
.
With 680
pull-up, the Fm+ rise time of 120 ns maximum
can be met with total bus loading up to 200 pF.
The logic level on RX is determined from the power supply voltage V
CC
of the chip. Logic
LOW is below 40 % of V
CC
, and logic HIGH is above 55 % of V
CC
(with a typical switching
threshold just slightly below half V
CC
).
PCA9600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 25 September 2015
4 of 32
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
TX is an open-collector output without ESD protection diodes to V
CC
. It may be connected
via a pull-up resistor to a supply voltage in excess of V
CC
, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I
2
C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I
2
C-bus pin SX is below 0.425 V. A
logic LOW at RX will cause I
2
C-bus pin SX to be pulled to a logic LOW level in accordance
with I
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I
2
C-bus by a LOW at RX is typically 0.64 V
when sinking 1 mA.
If the supply voltage V
CC
fails, then neither the I
2
C-bus nor the TX output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without V
CC
present. The input configuration on SX and RX also
presents no loading of external signals when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including V
CC
= 0 V.
Remark:
Two or more SX or SY I/Os must not be interconnected. The PCA9600 design
does not support this configuration. Bidirectional I
2
C-bus signals do not allow any
direction control pin so, instead, slightly different logic LOW voltage levels are used at
SX/SY to avoid latching of this buffer. A ‘regular I
2
C-bus LOW’ applied at the RX/RY of a
PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage
level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that
second PCA9600 will not recognize it as a ‘regular I
2
C-bus LOW’ and will not propagate it
to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example P82B96, PCA9511A,
PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatible
with, the normal I
2
C-bus logic voltage levels of I
2
C-bus master and slave chips, or even
TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O
pins use the standard I
2
C-bus logic voltage levels of all I
2
C-bus parts. There are
no
restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s,
for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the
common bus and the SX/SY side connected to the line card slave devices. For more
details see
Application Note AN10658, “Sending I
2
C-bus signals via long communication
cables”.
The PCA9600 is a direct upgrade of the P82B96 with the significant differences
summarized in
Table 4.
Table 4.
Detail
Supply voltage (V
CC
) range:
Maximum operating bus voltage
(independent of V
CC
):
Typical operating supply current:
Typical LOW-level input voltage on I
2
C-bus
(SX/SY side):
PCA9600
PCA9600 versus P82B96
PCA9600
2.5 V to 15 V
15 V
5 mA
0.5 V over
40 C
to +85
C
P82B96
2 V to 15 V
15 V
1 mA
0.65 V at 25
C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 25 September 2015
5 of 32
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