Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT12AI
GENERAL DESCRIPTION
Improved high-voltage, high-speed glass-passivated npn power transistor in a TO220AB envelope specially suited
for use in overhead/high frequency lighting ballast applications and converters, inverters, switching regulators,
motor control systems, etc.
QUICK REFERENCE DATA
SYMBOL
V
CESM
V
CEO
I
C
I
CM
P
tot
V
CEsat
I
Csat
t
f
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Collector saturation current
Inductive fall time
CONDITIONS
V
BE
= 0 V
TYP.
-
-
-
-
-
-
5
MAX.
1000
450
8
20
110
1.5
-
300
UNIT
V
V
A
A
W
V
A
ns
T
hs
≤
25 ˚C
I
C
= 5 A; I
B
= 0.86A
I
Con
= 5 A; I
Bon
= 1.0 A;T
j
≤
100˚C
PINNING - TO220AB
PIN
1
2
3
tab
base
collector
emitter
collector
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
c
b
1 23
e
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CESM
V
CEO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
V
BE
= 0 V
MIN.
-
-
-
-
-
-
-
-65
-
MAX.
1000
450
8
20
4
6
110
150
150
UNIT
V
V
A
A
A
A
W
˚C
˚C
T
hs
≤
25 ˚C
THERMAL RESISTANCES
SYMBOL
R
th j-hs
R
th j-a
PARAMETER
Junction to heatsink
Junction to ambient
CONDITIONS
with heatsink compound
in free air
TYP.
-
-
MAX.
1.15
60
UNIT
K/W
K/W
June 1997
1
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT12AI
STATIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
I
CES
I
CES
I
EBO
V
CEOsust
V
CEsat
V
BEsat
h
FE
h
FE
h
FEsat
PARAMETER
Collector cut-off current
1
CONDITIONS
MIN.
-
-
-
450
-
-
10
14
5.8
TYP.
-
-
-
-
-
-
18
20
10
MAX.
1.0
3.0
10
-
1.5
1.3
35
35
12.5
UNIT
mA
mA
mA
V
V
V
V
BE
= 0 V; V
CE
= V
CESMmax
V
BE
= 0 V; V
CE
= V
CESMmax
;
T
j
= 125 ˚C
Emitter cut-off current
V
EB
= 9 V; I
C
= 0 A
Collector-emitter sustaining voltage I
B
= 0 A; I
C
= 100 mA;
L = 25 mH
Collector-emitter saturation voltages I
C
= 5 A; I
B
= 0.86 A
Base-emitter saturation voltage
I
C
= 5 A; I
B
= 0.86 A
DC current gain
I
C
= 10mA; V
CE
= 5 V
I
C
= 1.0A; V
CE
= 5 V
I
C
= 5.0A; V
CE
= 1.5 V
DYNAMIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
t
on
t
s
t
f
PARAMETER
Switching times (resistive load)
Turn-on time
Turn-off storage time
Turn-off fall time
Switching times (inductive load)
t
s
t
f
Turn-off storage time
Turn-off fall time
CONDITIONS
I
Con
=5 A; I
Bon
= -I
Boff
= 1.0 A
TYP.
-
-
-
MAX.
1.0
4.0
0.8
UNIT
µs
µs
µs
µs
ns
I
Con
= 5 A; I
Bon
= 1.0 A; L
B
= 1
µH;
-V
BB
= 5 V; T
j
= 100 ˚C
1.9
150
2.5
300
IC / mA
+ 50v
100-200R
250
Horizontal
Oscilloscope
Vertical
300R
30-60 Hz
6V
1R
200
100
0
VCE / V
min
VCEOsust
Fig.1. Test circuit for V
CEOsust
.
Fig.2. Oscilloscope display for V
CEOsust
.
1
Measured with half sine-wave voltage (curve tracer).
June 1997
2
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT12AI
VCC
ICon
90 %
IC
RL
VIM
0
tp
IB
RB
T.U.T.
ts
toff
IBon
10 %
tf
t
T
-IBoff
t
Fig.3. Test circuit resistive load. VIM = -6 to +8 V
V
CC
= 250 V; tp = 20
µ
s;
δ
= tp / T = 0.01.
R
B
and R
L
calculated from I
Con
and I
Bon
requirements.
ICon
Fig.6. Switching times waveforms with inductive load.
90 %
90 %
VCC
IC
10 %
ts
ton
toff
IBon
10 %
tr
30ns
-IBoff
tf
LC
IB
IBend
VCL
LB
T.U.T.
CFB
-VBB
Fig.4. Switching times waveforms with resistive load.
Fig.7. Test circuit RBSOA. V
CC
= 150 V; -V
BB
= 5 V
L
C
= 200
µ
H; V
CL
≤
850 V; L
B
= 1
µ
H
PD%
Normalised Power Derating
VCC
120
110
100
90
80
LC
70
60
50
IBon
LB
T.U.T.
40
30
20
10
0
0
20
40
60
80
100
Tmb / C
120
140
-VBB
Fig.5. Test circuit inductive load.
V
CC
= 300 V; -V
BE
= 5 V;L
B
= 1 uH
Fig.8. Normalised power dissipation.
PD% = 100
⋅
PD/PD
25˚C
= f (T
mb
)
June 1997
3
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT12AI
VBEsat / V
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
1
10
IC / A
Fig.9. Typical base-emitter saturation voltage.
V
BEsat
= f(I
C
); parameter I
C
/I
B
0.1
IC/IB=
8
10
12
1
0.9
0.8
0.7
0.6
1.2
VBEsat / V
Tj = 25 C
Tj = 125 C
1.1
Tj = 25 C
Tj = 125 C
IC =
6A
3A
2A
0
0.4
0.8
1.2
IB / A
1.6
2
2.4
Fig.11. Typical base-emitter saturation voltage.
V
BEsat
= f(I
B
); parameter I
C
VCEsat / V
10
Tj = 25 C
Tj = 125 C
VCEsat / V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
1
IC / A
10
Tj = 25 C
Tj = 125 C
IC/IB=
12
10
8
5
6A
1
4A
IC=2A
0.1
Fig.10. Typical collector-emitter saturation voltage.
V
CEsat
= f(I
C
); parameter I
C
/I
B
1
10
IB / A
Fig.12. Typical collector-emitter saturation voltage.
VCEsat = f(IB); parameter IC
0.1
June 1997
4
Rev 1.000
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUT12AI
IC / A
100
h
FE
100
ICMmax
10
5V
ICmax
10
II
1V
1
Tj = 25 C
Tj = 125 C
I
0.1
DC
1
0.01
0.1
IC / A
1
10
Fig.15. Typical DC current gain. hFE = f(IC)
parameter VCE
0.01
1
10
100
1000
VCE / V
Fig.13. Forward bias safe operating area. T
mb
= 25˚C
I
II
NB:
Region of permissible DC operation.
Extension for repetitive pulse operation.
Mounted with heatsink compound and
30
±
5 newton force on the centre of the
envelope.
1E+01
IC / A
8
7
Zth / (K/W)
BUX100
6
5
4
3
2
1
0
1E+00
0.5
0.2
0.1
1E-01
0.05
0.02
D=0
1E-02
0
200
400
600
800
1000
P
D
tp
D=
t
p
T
t
T
1E-05
1E-03
t/s
1E-01
1E+01
VCE / V
Fig.14. Reverse bias safe operating area. T
j
≤
T
j max
Fig.16. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
June 1997
5
Rev 1.000
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