PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt
and reset
Rev. 9 — 8 November 2017
Product data sheet
1. General description
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General
Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for
I
2
C-bus/SMBus applications and was developed to enhance the NXP Semiconductors
family of I
2
C-bus I/O expanders. I/O expanders provide a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),
input, output and polarity inversion (active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with the Polarity inversion
register. All registers can be read by the system master.
The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the
internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are
held LOW, replacement of A2 with RESET and a different address range.
The PCA9539; PCA9539R open-drain interrupt output is activated when any input state
differs from its corresponding input port register state and is used to indicate to the system
master that an input state has changed.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCA9539, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I
2
C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to V
DD
. In the PCA9539R however, only the device state machine is
initialized by the RESET pin and the internal general-purpose registers remain
unchanged. Using the PCA9539R RESET pin will only reset the I
2
C-bus interface should
it be stuck LOW to regain access to the I
2
C-bus. This allows the I/O pins to retain their last
configured state so that they can keep any lines in their previously defined state and not
cause system errors while the I
2
C-bus is being restored.
Two hardware pins (A0, A1) vary the fixed I
2
C-bus address and allow up to four devices to
share the same I
2
C-bus/SMBus.
2. Features and benefits
16-bit I
2
C-bus GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V
for PCA9539PW/Q900 and PCA9539RPW/Q900)
5 V tolerant I/Os
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Polarity inversion register
Active LOW interrupt output
Active LOW reset input
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Offered in three different packages: SO24, TSSOP24, and HVQFN24
3. Ordering information
Table 1.
Ordering information
Topside
marking
9539
539R
PCA9539D
Package
Name
HVQFN24
HVQFN24
SO24
Description
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
4
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
4
0.85 mm
plastic small outline package; 24 leads;
body width 7.5 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT616-1
SOT616-1
SOT137-1
SOT355-1
SOT355-1
SOT355-1
SOT355-1
Type number
PCA9539BS
PCA9539RBS
PCA9539D
PCA9539PW
PCA9539PW/Q900
[1]
PCA9539RPW
PCA9539PW TSSOP24
PCA9539PW TSSOP24
PA9539RPW TSSOP24
PCA9539RPW/Q900
[1]
PA9539RPW TSSOP24
[1]
PCA9539PW/Q900 and PCA9539RPW/Q900 are AEC-Q100 compliant. Contact
I2C.support@nxp.com
for PPAP.
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9539BS,115
PCA9539BS,118
PCA9539BSHP
Package
Packing method
Minimum Temperature
order
quantity
1500
6000
6000
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9539BS
HVQFN24 Reel 7” Q1/T1
*standard mark SMD
[1]
HVQFN24 Reel 13” Q1/T1
*standard mark SMD
[1]
HVQFN24 Reel 13” Q2/T3
*standard mark SMD
[2]
All information provided in this document is subject to legal disclaimers.
PCA9539_PCA9539R
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 9 — 8 November 2017
2 of 39
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Table 2.
Ordering options
…continued
Orderable
part number
PCA9539RBS,118
PCA9539D,112
Package
Packing method
Minimum Temperature
order
quantity
6000
1200
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9539RBS
PCA9539D
HVQFN24 Reel 13” Q1/T1
*standard mark SMD
[1]
SO24
Standard marking *
IC’s tube -
DSC bulk pack
Reel 13” Q1/T1
*standard mark SMD
[1]
PCA9539D,118
PCA9539PW
PCA9539PW,112
SO24
1000
1575
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
TSSOP24 Standard marking *
IC’s tube -
DSC bulk pack
TSSOP24 Reel 13” Q1/T1
*standard mark SMD
[1]
PCA9539PW,118
PCA9539PW/Q900
PCA9539RPW
2500
2500
2500
2500
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
PCA9539PW/Q900,118 TSSOP24 Reel 13” Q1/T1
*standard mark SMD
[1]
PCA9539RPW,118
TSSOP24 Reel 13” Q1/T1
*standard mark SMD
[1]
TSSOP24 Reel 13” Q1/T1
*standard mark SMD
[1]
PCA9539RPW/Q900 PCA9539RPWJ
[1]
[2]
Pin 1 in Quadrant 1; see
Figure 2.
Pin 1 in Quadrant 2; see
Figure 3.
3.1.1 Pin 1 quadrant indication
way into
the reel
Q1
Q2
Q3
Q4
Quadrant designations
Q1 = upper left
Q2 = upper right
Q3 = lower left
Q4 = lower right
round
sprocket
holes
aaa-010180
Fig 1.
Carrier tape pin 1 quadrant designations
Fig 2.
Pin 1 in Q1
Fig 3.
Pin 1 in Q2
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 9 — 8 November 2017
3 of 39
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