PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the
right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to
supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other
than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described
herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
2)
All other trademarks are of their respective companies.
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2015 REVISION 1.13
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
REVISION HISTORY
Date
07/10/04
07/26/04
Revision Number
0.03
1.00
Description
Initial release of preliminary specification
Initial release of specification to the web
Updated Power Dissipation in section 17.9
Updated T
DELAY
in sections 17.4 and 17.5
Revised V
IH
parameter in section 17.2
Updated with Industrial temperature range support
-Product Features section (Introduction)
-Part number ordering information in section 18.2
Corrected ambient temperature maximum rating to -40°C to 85°C
(from 0°C to 85°C) in section 17.1
Removed ‘Advance Information’ from headings
Removed ‘solutions@pericom.com’ link
04/08/15
04/20/05
1.10
04/26/05
03/07/06
1.11
1.12
1.13
Corrected unit measure for TGH in section 17.7 from nx to ns
Updated Ordering Information
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2015 REVISION 1.13
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
TABLE OF CONTENTS
LIST OF TABLES...............................................................................................................................................10
LIST OF FIGURES.............................................................................................................................................10
INTRODUCTION ...............................................................................................................................................11
1
SIGNAL DEFINITIONS ...........................................................................................................................12
1.1
SIGNAL TYPES ................................................................................................................................12
1.2
SIGNALS ...........................................................................................................................................12
1.2.1
PRIMARY BUS INTERFACE SIGNALS ........................................................................................12
1.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ...................................................14
1.2.3
SECONDARY BUS INTERFACE SIGNALS ..................................................................................15
1.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION..................................................17
1.2.5
CLOCK SIGNALS..........................................................................................................................17
1.2.6
MISCELLANEOUS SIGNALS........................................................................................................18
1.2.7
GENERAL PURPOSE I/O INTERFACE SIGNALS.......................................................................19
1.2.8
JTAG BOUNDARY SCAN SIGNALS .............................................................................................19
1.2.9
POWER AND GROUND ...............................................................................................................19
1.3
PIN LIST ............................................................................................................................................20
2
SIGNAL DEFINITIONS ...........................................................................................................................23
2.1
2.2
2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
TYPES OF TRANSACTIONS...........................................................................................................23
SINGLE ADDRESS PHASE .............................................................................................................24
DUAL ADDRESS PHASE ................................................................................................................24
DEVICE SELECT (DEVSEL#) GENERATION...............................................................................24
DATA PHASE ...................................................................................................................................24
WRITE TRANSACTIONS ................................................................................................................25
MEMORY WRITE TRANSACTIONS .............................................................................................25
MEMORY WRITE AND INVALIDATE..........................................................................................26
DELAYED WRITE TRANSACTIONS ............................................................................................26
WRITE TRANSACTION ADDRESS BOUNDARIES......................................................................27
BUFFERING MULTIPLE WRITE TRANSACTIONS ....................................................................27
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................28
READ TRANSACTIONS ..................................................................................................................28
PREFETCHABLE READ TRANSACTIONS ..................................................................................28
NON-PREFETCHABLE READ TRANSACTIONS.........................................................................28
READ PREFETCH ADDRESS BOUNDARIES .............................................................................29
DELAYED READ REQUESTS.......................................................................................................29
DELAYED READ COMPLETION ON TARGET BUS ..................................................................30
DELAYED READ COMPLETION ON INITIATOR BUS ..............................................................30
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................31
CONFIGURATION TRANSACTIONS ............................................................................................31
TYPE 0 ACCESS TO PI7C8154A ..................................................................................................32
TYPE 1 TO TYPE 0 CONFIGURATION .......................................................................................32
TYPE 1 TO TYPE 1 FORWARDING .............................................................................................34
SPECIAL CYCLES.........................................................................................................................34
64-BIT OPERATION.........................................................................................................................35
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154B .............................................35
64-BIT TRANSACTIONS – ADDRESS PHASE .............................................................................35
64-BIT TRANSACTIONS – DATA PHASE ....................................................................................36
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154B ...............................................................36
64-BIT TRANSACTIONS – SUPPORT DURING RESET..............................................................37
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2015 REVISION 1.13
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