Mixed-Signal Dual-Core Control Processor
with ARM Cortex-M4/M0 and 16-bit ADCs
Preliminary Technical Data
SYSTEM FEATURES
Up to 240 MHz ARM Cortex-M4 with floating-point unit with
up to 160K Byte zero-wait-state ECC SRAM
Safety based dual independent- core concept
Up to 1M Byte high performance ECC FLASH that can execute
instructions at near SRAM speed
Highest precision, low latency 31-channel analog front end
100 MHz ARM Cortex-M0 supervisor core with 32K Byte zero
wait state ECC SRAM
Single 3.3 V power supply
Static memory controller (SMC) with asynchronous memory
interface that supports 8-bit and 16-bit memories
Heightened, 24-channel precision pulse PWM unit
Four 3
rd
or 4
th
order SINC filters for glueless connection of
sigma-delta modulators
Hardware based harmonic analysis engine (HAE)
Logic block array (LBA)
FFT signal spectrum monitor
ADSP-CM411F/412F/413F/416F/417F/418F/419F
MATH accelerator and FSAT blocks
Two CAN 2.0B interfaces and up to five UARTs
Two serial peripheral interface (SPI compatible) ports
Four encoder interfaces, two with frequency division
Package options:
176-lead (24 mm × 24 mm) LQFP_EP package
210-ball (15 mm × 15 mm) CSP_BGA package
ANALOG FRONT END
16-bit A/D converter with 24 multiplexed inputs, supporting
6-way simultaneous sampling and
6-channel conversion in 1.4μ seconds
Independent 14-bit, 7-channel auxiliary ADC with seven
inputs
ADC controllers (ADCC0/ADCC1) and DAC controller (DACC0)
12-bit D/A converter
Up to three 2.5 V precision voltage reference outputs
(For details, see
ADC/DAC/Voltage Reference/Comparator
Specifications.)
SYSTEM
CONTROL
BLOCKS
PERIPHERALS
CRC
OCU
FAULT
MANAGEMENT
SECURITY
SYSTEM
CONTROL
BLOCKS
JTAG, SWD,
CoreSight™ TRACE
FAULT
MANAGEMENT
SECURITY
EVENT
CONTROL
SYSTEM
WATCHDOGS
PLL & POWER
MANAGEMENT
EVENT
CONTROL
SYSTEM
WATCHDOGS
Cortex-M0
SRAM
32K BYTE
SRAM
MAILBOX
Cortex-M4
MATH
CORDIC
FSAT
1× TWI / I
2
C
24× PWM
8× TIMER
1× CAN
4× UART
1× SPI
1x SPORT
FLASH
UP TO
1M BYTE
FLASH
SRAM
UP TO
160K BYTE
SRAM
LOCAL FABRIC
LOCAL FABRIC
PERIPHERALS
8× TIMER
SYSTEM FABRIC
SYSTEM FABRIC
STATIC
MEMORY
CONTROLLER
(ASYNC I/F)
GPIO (14)
1× CAN
1× UART
1× SPI
AFE
ADCC0
ADC0
AFE
ADCC1
FOCP
ADC1/2
DAC
LBA
DACC0
HAE
H/W ENHANCE
FFT
SINC
FILTERS
Figure 1. ADSP-CM41xF Block Diagram
Rev. PrC
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GPIO (59)
ADSP-CM411F/412F/413F/416F/417F/418F/419F
TABLE OF CONTENTS
General Description ................................................. 3
Analog Front End ................................................. 4
Dual-Core System Architecture .............................. 10
EmbeddedICE .................................................... 13
Processor Infrastructure ....................................... 13
Memory Architecture .......................................... 17
System Acceleration ............................................ 19
Security Features ................................................ 19
Security Features Disclaimer .................................. 19
Safety Features ................................................... 19
Processor Peripherals ........................................... 21
Clock and Power Management ............................... 24
System Debug .................................................... 26
Development Tools ............................................. 27
Additional Information ........................................ 27
Related Signal Chains .......................................... 27
ADSP-CM41xF Detailed Signal Descriptions ................ 28
176-Lead LQFP_EP Signal Descriptions ...................... 31
GPIO Multiplexing for 176-Lead LQFP_EP Package ...... 38
210-Ball CSP_BGA Signal Descriptions ....................... 41
GPIO Multiplexing for 210-Ball CSP_BGA Package ....... 47
ADSP-CM41xF Designer Quick Reference ................... 50
Preliminary Technical Data
Specifications ........................................................ 60
Operating Conditions ........................................... 60
Electrical Characteristics ....................................... 63
ADC/DAC/Voltage Reference/Comparator
Specifications .................................................. 65
Flash Specifications .............................................. 71
Absolute Maximum Ratings ................................... 72
ESD Caution ...................................................... 72
Package Information ............................................ 72
Timing Specifications ........................................... 73
Processor Test Conditions ................................... 106
Output Drive Currents ....................................... 106
Environmental Conditions .................................. 108
ADSP-CM41xF 176-Lead LQFP_EP Lead
Assignments .................................................... 109
Numerical by Lead Number.................................. 109
Alphabetical by Pin Name ................................... 111
ADSP-CM41xF 210-Ball CSP_BGA Ball Assignments ... 113
Numerical by Ball Number .................................. 113
Alphabetical by Pin Name ................................... 115
Outline Dimensions .............................................. 118
Pre Release Products .......................................... 120
REVISION HISTORY
3/2018—Rev. PrB to Rev. PrC
Changes to
System Features ........................................ 1
Changes to
ADSP-CM41xF Block Diagram .................... 1
Changes to
Product Features ...................................... 3
Changes to
PWM Pin Programmable Drive Strength ...... 16
Added
Floating-Point Saturation (FSAT) Unit .............. 23
Changes to
Internal Voltage Regulator Circuit .............. 26
Changes to
ADSP-CM41xF Detailed Signal Descriptions . 28
Changes to
ADSP-CM412F/CM413F/CM416F/CM417F 176-
Lead LQFP_EP Signal Descriptions ............................ 31
Changes to
ADSP-CM411F/CM418F/CM419F 210-Ball
CSP_BGA Signal Descriptions .................................. 41
Changes to
ADSP-CM41xF Designer Quick Reference .... 50
Changes to
Operating Conditions .............................. 60
Changes to
Clock Related Operating Conditions ........... 61
Changes to
Electrical Characteristics ........................... 63
Changes to
ADC Specifications –ADC1, ADC2 ............. 65
Changes to
DAC Specifications .................................. 67
Changes to
Comparator Specifications ........................ 68
Added Table to
Flash Specifications ............................ 71
Changes to
Absolute Maximum Ratings ....................... 72
Changes to
Clock and Reset Timing ............................ 73
Changes to
Power-Up Reset Timing ............................ 74
Changes to
Power-Down Timing ............................... 75
Changes to
SPI Port—Master Timing .......................... 87
Added Table 55, Figure 63, Figure 64, and Figure 65 to
PWM— Heightened Precision (HP) Mode Timing ......... 99
Changes to
Serial Wire Debug (SWD) Timing ............. 103
Changes to
Debug Interface (JTAG Emulation Port) Timing .......... 104
Added
ADC Timing .............................................. 105
Added Figure 76,
Capacitive Loading ........................ 107
Changes to
Environmental Conditions ...................... 108
Rev. PrC |
Page 2 of 120 |
March 2018
Preliminary Technical Data
GENERAL DESCRIPTION
ADSP-CM411F/412F/413F/416F/417F/418F/419F
By integrating a rich set of industry leading system functions
and memory (shown in
Table 1),
the ADSP-CM41xF mixed-
signal control processors are the platform of choice for next
generation applications that require RISC (reduced instruction
set computing) programmability and leading edge signal pro-
cessing in one integrated package. These applications span a
wide array of markets in power conversion and include solar PV
inverters, motor/power control, and battery charging/control.
Table 1
provides the product features shown by generic model.
The ADSP-CM41xF family of mixed-signal control processors
is based on the ARM
®
Cortex
®
-M4 processor core with floating-
point unit operating at frequencies up to 240 MHz and the
ARM
®
Cortex
®
-M0 processor core operating at frequencies up
to 100 MHz. The processors integrate up to 192K Bytes of
SRAM memory with ECC, up to 1M Byte of flash memory with
ECC, accelerators and peripherals optimized for motor control
and photo-voltaic (PV) inverter control, and an analog module
consisting of up to two 16-bit SAR-type ADCs, one 14-bit ADC,
and one 12-bit DAC. The ADSP-CM41xF family operates from
a single voltage supply, generating its own internal voltage sup-
plies using internal voltage regulators and a simple external
transistor circuit.
Table 1. Product Features
Generic
Package Type
Processor
Processor Type
M4 Processor Feature Code
M4 L1 SRAM (KB)
1
M0 L1 SRAM (KB)
2, 3
M4 L1 Flash (KB)
M4 Core Clock (MHz)
M0 Core Clock (MHz)
4
Analog Functions
16-bit ADC Simultaneous Sampling
16-bit ADC Inputs
16-bit ADC ENOB
14-bit ADC Inputs
DAC Outputs
FOCP (Fast Overcurrent Protection)
Digital Functions
GPIO (General-Purpose I/O)
PWM (Pulse Width Modulator Out)
HAE (Harmonics Analysis Engine)
CORDIC
FFT Arcing Detection
SINC3 or SINC4 Filter Inputs
CAN
UART
SPI
I
2
C
GP Timers (General Purpose)
SPORTs (Serial Ports)
16-Bit EBIU
1
2
ADSP-
CM411F
210-Ball BGA
ADSP-
CM412F
ADSP-
ADSP-
CM413F
CM416F
176-Lead LQFP
ADSP-
CM417F
ADSP-
ADSP-
CM418F
CM419F
210-Ball BGA
SINGLE CORE:
ARM Cortex-M4
A
B
A
B
B
128
128 128
128 128
32
32
32
32
32
256
256 256 256 256
180
240 180 240 240
N/A
N/A N/A N/A N/A
C
160
32
512
240
N/A
DUAL CORE:
ARM Cortex-M4, ARM Cortex-M0
B
C
C
D
B
C
C
D
128 160 160 160 128 160 160 160
32
32
32
32
32
32
32
32
256 512 512 1024 256 512 512 1024
240 240 240 240 240 240 240 240
100 100 100 100 100 100 100 100
6-Way at 4.4 Msps
24
24
11+
13+
7
7
1
1
3
3
73
24
1
1
1
4
2
5
2
1
16
1
1
73
24
1
1
1
4
2
5
2
1
16
1
1
24
11+
7
1
3
73
24
0
1
0
4
2
3
2
1
8
1
1
24
11+
7
1
3
73
24
0
1
0
4
2
3
2
1
8
1
1
3-Way at 2.2 Msps
24
13+
7
1
3
73
24
1
1
0
4
2
5
2
1
8
1
1
24
11+
7
1
3
73
24
1
1
1
4
2
5
2
1
16
1
1
24
13+
7
1
3
73
24
1
1
1
4
2
5
2
1
16
1
1
M4 L1 SRAM memory blocks are accessible from the M0 core as an L2 memory space. Memory protection features are available to regulate access.
M0 L1 SRAM memory block is available on all models and variants.
3
M0 L1 SRAM memory block is accessible from the M4 core as an L2 memory space.
4
N/A means not applicable.
Rev. PrC |
Page 3 of 120 |
March 2018
ADSP-CM411F/412F/413F/416F/417F/418F/419F
ANALOG FRONT END
The processors contain one ADC attached to the ARM Cortex-
M0 core and two ADCs plus one DAC attached to the ARM
Cortex-M4 core. Control of these data converters is simplified
by two powerful on-chip analog-to-digital conversion control-
lers (ADCC) and a digital-to-analog conversion controller
(DACC). The ADCC and DACC are integrated seamlessly into
the software programming model, and they efficiently manage
the configuration and real-time operation of the ADCs and
DACs.
For technical details, see
ADC/DAC/Voltage Reference/Com-
parator Specifications.
The ADCC of the ARM Cortex-M4 core provides the mecha-
nism to control timing and execution of analog sampling events
on the ADCs. The ADCC supports up to 6-channel simultane-
ous sampling (3x each on ADC1, ADC2) and can deliver 6
channels of consecutively and simultaneously sampled ADC
data to memory in 1.4μs, or 16 channels sampled consecutively
in simultaneous pairs to memory in 3.0μs. Conversion data
from the ADCs may be either routed via DMA to memory, or to
a destination register read by the processor, or written directly
to any destination register without processor intervention (for
example to the FFT). The ADCC can be configured so that the
two ADCs sample and convert both sets of analog inputs simul-
taneously or at different times and may be operated in
asynchronous or synchronous modes. Full time-matching per-
formance can be achieved in synchronous mode.
Likewise, the DACC interfaces to one externally connected
DAC and two internally connected threshold DACs, and has the
purpose of managing those DACs. Conversion data to the
DACs may be either routed from memory through DMA, or
from a source register via the processor.
Functional operation and programming for the ADCC and
DACC are described in detail in the
ADSP-CM41x Mixed-Sig-
nal Control Processor with ARM Cortex-M4/ARM Cortex-M0
and 16-bit ADCs Hardware Reference.
ADC and DAC features and performance specifications differ
by processor model. Simplified block diagrams of the ADCC,
DACC and the ADCs and DACs are shown in
Figure 2,
Figure 3,
and
Figure 4.
Preliminary Technical Data
Fast Over Current Protection (FOCP)
The fast over current protection (FOCP) block is required to
overcome the sampling rate requirement for certain inputs.
There are three comparators available. The input of each com-
parator is connected internally to inputs A0, B0, and C0. The
comparators have a common upper threshold (LIMIT_U) and a
common lower threshold (LIMIT_L), which is set by the inter-
nal 8-bit DACs. COMP_OUT_A/B/C outputs are user
accessible. If one or more comparators are signaling LIMT
(availability of COMP_OUT_A/B/C), the AFE asserts an inter-
rupt to the processor.
Analog Front End (AFE) Module
The ADC module contains two primary ADCs (ADC1 and
ADC2), each with three multiplexed track and hold (T/H) units,
which can each sample up to 8 analog inputs per T/H. In addi-
tion, the ADC module also contains a fully independent
monitor ADC (ADC0) preceded by a 7-input channel multi-
plexer. See
ADC Specifications –ADC0, ADC1, ADC2
for
detailed performance specifications.
The voltage input range requirement for analog inputs is 0 V to
3.0 V. All analog inputs are of the same single-ended design. As
with all single-ended inputs, signals from high impedance
sources are the most difficult to control, and depending on the
electrical environment, may require an external buffer circuit
for signal conditioning (see
Figure 7).
Precharge buffers are
included to assist the external buffers in charging the 25pF input
capacitor. The precharge feature may be disabled in software.
DAC Module
The DAC is a 12-bit, low power, string DAC design. The output
of the DAC is buffered, and can drive an R/C load to either
ground or V
DD_ANA
. See
DAC Specifications
for detailed perfor-
mance specifications.
Considerations for Best Converter Performance
As with any high performance analog/digital circuit, to achieve
best performance, good circuit design and board layout prac-
tices should be followed. The power supply and its noise bypass
(decoupling), ground return paths and pin connections, and
analog/digital routing channel paths and signal shielding, are all
of first-order consideration. For application hints of design best
practice, see
Figure 5
and
Figure 6
and the
ADSP-CM41x
Mixed-Signal Control Processor with ARM Cortex-M4/ARM
Cortex-M0 and 16-bit ADCs Hardware Reference.
For more
information about the VREG circuit, see
Figure 18,
Internal
Voltage Regulator Circuit.
Rev. PrC |
Page 4 of 120 |
March 2018
Preliminary Technical Data
ADSP-CM411F/412F/413F/416F/417F/418F/419F
M0 MICROCONTROLLER
ADCC0
M4 MICROCONTROLLER
ADCC1
DACC0
MONITOR ADC LOCAL CONTROLLER
PRIMARY ADC/DAC/COMP
LOCAL CONTROLLER
ADC_VIN_D0
T/H
ADC_VIN_D6
14-BIT
ADC 0
VREF0
BUF
BANDGAP
REFCAP0
SEE NOTE.
8-BIT
DAC
12-BIT
DAC 0
DAC0_VOUT
COMP A
COMP_OUT_A
COMP_OUT_B
COMP_OUT_C
COMP B
COMP C
ADC_VIN_A0
A1
ADC_VIN_A3
ADC_VIN_B0
T/H
16-BIT
ADC 1
8-BIT
DAC
B1
ADC_VIN_B3
ADC_VIN_C0
T/H
VREF1
C1
ADC_VIN_C3
T/H
BUF
BUF
BANDGAP
REFCAP1
VREF2
ADC_VIN_A4
A2
ADC_VIN_A7
ADC_VIN_B4
T/H
16-BIT
ADC 2
NOTE:
THE ADC0 IS POWERED AND OPERATED INDEPENDENTLY OF THE
M4 MICROCONTROLLER, ADC1, ADC2, DAC0, AND COMP A, COMP B,
COMP C. THIS IS A PRIMARY SAFETY FEATURE OF THE ADSP-CM418F
AND ADSP-CM419F MIXED-SIGNAL CONTROL PROCESSORS.
B2
ADC_VIN_B7
ADC_VIN_C4
T/H
C2
ADC_VIN_C7
T/H
Figure 2. Analog Front End Block Diagram ADSP-CM418F/CM419F Dual-Core, 6-Way Sampling
Rev. PrC |
Page 5 of 120 |
March 2018
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