)6)6)6)6
X
T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
1.0
•
•
•
Features
2.0
Description
Generates up to eighteen low-skew, non-inverting
clocks from one clock input
Supports up to four SDRAM DIMMs
2
Uses either I C
™
-bus or SMBus serial interface with
Read and Write capability for individual clock output
control
Output enable pin tristates all clock outputs to facili-
tate board testing
Clock outputs skew-matched to less than 250ps
Less than 5ns propagation delay
Output impedance: 17Ω at 0.5V
DD
Serial interface I/O meet I C specifications; all other
I/O are LVTTL/LVCMOS-compatible
Five differerent pin configurations available:
•
•
•
•
FS6050: 18 clock outputs in a 48-pin SSOP
FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
FS6053: 13 clock outputs in a 28-pin SOIC
FS6054: 14 clock outputs in a 28-pin SOIC
2
•
•
•
•
•
•
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
®
as Intel Pentium II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
2
Under I C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
SDRAM_11
SDRAM_10
SDRAM_17
SDRAM_9
SDRAM_8
(reserved)
(reserved)
VDD
VSS
VSS
27
VSS_I
2
C
26
23
VDD
VDD
VDD
VDD
VSS
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Figure 1: Block Diagram (FS6050)
10
FS6050
11
12
13
14
15
16
17
18
19
20
21
22
VDD
(reserved)
(reserved)
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_7
SDRAM_16
VDD
VDD
VDD
VDD
CLK_IN
VDD
VDD_I
2
C
VSS
VSS
VSS
VSS
VSS
SDRAM_(0:1)
VDD_I
2
C
VSS
VDD
SDA
Serial
Interface
SCL
VSS_I
2
C
18
SDRAM_(2:3)
VSS
VDD
48-pin SSOP
SDRAM_(4:5)
VSS
VDD
SDRAM_(6:7)
CLK_IN
VSS
VDD
Figure 3: Pin Configuration (FS6051)
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
SDRAM_17
VDD
VDD
VDD
VSS
VSS
VSS_I
2
C
VSS
OE
SCL
SDRAM_(8:9)
VSS
VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
VSS
VDD
SDRAM_(12:13)
VSS
VDD
FS6051
10
11
12
13
14
1
2
3
4
5
6
7
8
9
SDRAM_(14:15)
VSS
VDD
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_16
VDD_I
2
C
VDD
VDD
CLK_IN
VDD
SDRAM_16
OE
VSS
VDD
SDRAM_17
VSS
28-pin SOIC, SSOP
FS6050
Additional pin configurations are noted on Page 2.
,62
Intel and Pentium are registered trademarks of Intel Corporation. I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
tions as may be required to permit improvements in the design of its products.
4.5.99
SDA
VSS
VSS
VSS
15
SDRAM_(10:11)
SDA
24
1
2
3
4
5
6
7
8
9
25
SCL
OE
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X
T
April 1999
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN (FS6050)
11
25
24
4
5
8
9
13
14
17
18
31
32
35
36
40
41
44
45
21
28
38
3, 7, 12, 16,
20, 29, 33, 37,
42, 46
23
6, 10, 15, 19,
22, 27, 30, 34,
39, 43
26
1, 2, 47, 48
PIN (FS6051)
9
15
14
2
3
6
7
-
-
-
-
-
-
-
-
22
23
26
27
11
18
20
1, 5, 10, 19,
24, 28
13
4, 8, 12, 17,
21, 25
16
-
PIN (FS6053)
9
15
14
2
3
6
7
-
-
10
11
18
19
-
-
22
23
26
27
12
-
-
1, 5, 20, 24,
28
13
4, 8, 17, 21,
25
16
-
PIN (FS6054)
9
15
14
2
3
6
7
-
-
10
11
18
19
-
-
22
23
26
27
12
17
20
1, 5, 24, 28
13
4, 8, 21, 25
16
-
TYPE
DI
DI
U
DI
U
O
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DI
U
P
P
P
P
-
NAME
CLK_IN
SCL
SDA
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_7
SDRAM_8
SDRAM_9
SDRAM_10
SDRAM_11
SDRAM_12
SDRAM_13
SDRAM_14
SDRAM_15
SDRAM_16
SDRAM_17
OE
VDD
VDD_I
2
C
VSS
VSS_I
2
C
(reserved)
DESCRIPTION
Clock input for SDRAM clock outputs
Serial clock input
Serial data input/output
SDRAM clock outputs (Byte 0)
SDRAM clock outputs (Byte 1)
SDRAM feedback clock outputs (Byte 2)
Output enable tristates all clock outputs when low
3.3V ± 5% power supply for SDRAM clock buffers
3.3V ± 5% power supply for serial communications
Ground for SDRAM clock buffers
Ground for serial communications
Reserved
Figure 4: Pin Configuration (FS6053)
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
SDRAM_9
SDRAM_8
VSS_I
2
C
VDD
VDD
VDD
VSS
VSS
VSS
SCL
Figure 5: Pin Configuration (FS6054)
SDRAM_13
SDRAM_15
SDRAM_14
SDRAM_12
SDRAM_9
SDRAM_17
17
SDRAM_8
VDD
VDD
VSS
VSS
VSS_I
2
C
16
13
28
27
26
25
24
23
22
21
20
OE
19
18
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FS6053
10
11
12
13
14
1
2
3
4
5
FS6054
10
11
12
14
6
7
8
9
1
2
3
4
5
6
7
8
9
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_6
SDRAM_7
SDRAM_16
VDD_I
2
C
VDD
VDD
CLK_IN
VSS
SDRAM_16
SDRAM_3
SDRAM_6
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_7
CLK_IN
VDD
VDD
VDD_I
2
C
SDA
SDA
VSS
VSS
VSS
15
SCL
4.5.99
,62
2
)6)6)6)6
X
T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
3.0
Programming Information
3.2
Register Programming
Table 2: Clock Enable
CONTROL INPUTS
OE
0
1
CLOCK OUTPUTS (MHz)
SDRAM_0:17
tristate
CLK_IN
A logic-one written to a valid bit location turns on the as-
signed output clock. Likewise, a logic-zero written to a
valid bit location turns off the assigned output clock.
Any unused or reserved register bits should be cleared to
zero.
Serial bits are written to this device in the order shown in
Table 3.
Table 3: Register Summary
3.1
Power-Up Initialization
SERIAL BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DATA BYTE
CLOCK OUTPUT
SDRAM_7
SDRAM_6
SDRAM_5
All outputs are enabled and active upon power-up, and all
output control register bits are initialized to one.
The outputs must be configured at power-up and are not
expected to be configured during normal operation. Inac-
tive outputs are held low and are disabled from switching.
(MSB)
Byte 0
SDRAM Control Register 0
SDRAM_4
SDRAM_3
SDRAM_2
SDRAM_1
3.1.1 Unused Outputs
Outputs that are not used in versions of this device with a
reduced pinout are still operational internally. To reduce
power dissipation and crosstalk effects from the unloaded
outputs, it is recommended that these outputs be shut off
via the Control Registers.
(LSB)
(MSB)
SDRAM_0
SDRAM_15
SDRAM_14
SDRAM_13
Byte 1
SDRAM Control Register 1
SDRAM_12
SDRAM_11
SDRAM_10
SDRAM_9
(LSB)
(MSB)
SDRAM_8
SDRAM_17
SDRAM_16
Reserved
Byte 2
SDRAM Control Register 2
Reserved
Reserved
Reserved
Reserved
(LSB)
Reserved
4.5.99
,62
3
)6)6)6)6
X
T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
4.0
Dual Serial Interface Control
This integrated circuit is a read/write slave device that
2
supports both the Inter IC Bus (I C-bus) and the System
Management Bus (SMBus) two-wire serial interface pro-
tocols. The unique device address that is written to the
device determines whether the part expects to receive
2
SMBus commands or I C commands. Since SMBus is
2
derived from the I C-bus, the protocol for both bus types
is very similar.
In general, the bus has to be controlled by a master de-
vice that generates the serial clock SCL, controls bus
access, and generates the START and STOP conditions
while the device works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated. A device that
sends data onto the bus is defined as the transmitter, and
a device receiving data as the receiver.
Bus logic levels and timing parameters noted herein fol-
2
low I C-bus convention. Logic levels are based on a per-
centage of VDD. A logic-one corresponds to a nominal
voltage of VDD, while a logic-zero corresponds to ground
(VSS).
4.1.4 Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the data registers are filled will overflow from
the last register into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
4.1.5 Acknowledge
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to allow the master to
generate a STOP condition.
4.1
Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line when the clock line is
high is interpreted by the device as a START or STOP
2
condition. Both I C-bus and SMBus protocols define the
following conditions on the bus. Refer to Figure 12: Bus
Timing Data for more information.
4.2
Bus Operation and Commands
4.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
4.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
4.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
All programmable registers can be accessed via the bi-
directional two wire digital interface. The device accepts
the Random Register Read/Write and the Sequential
2
Register Read/Write I C commands. The device also
supports the Block Read/Write SMBus commands.
4.2.1 I
2
C-bus and SMBus Device Addressing
After generating a START condition, the bus master
broadcasts a seven-bit device address followed by a R/W
2
bit. Note that every device on an I C-bus or SMBus must
have a unique address to avoid bus conflicts.
For an SMBus interface, the address of the device is:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
4.5.99
,62
5
京公网安备 11010802033920号
EEWORLD
