C0G (NP0) Dielectric
General Specifications
C0G (NP0) is the most popular formulation of the
“temperature-compensating,” EIA Class I ceramic materials.
Modern C0G (NP0) formulations contain neodymium, samarium
and other rare earth oxides.
C0G (NP0) ceramics offer one of the most stable capacitor
dielectrics available. Capacitance change with temperature
is 0 ±30ppm/°C which is less than ±0.3% C from -55°C to
+125°C. Capacitance drift or hysteresis for C0G (NP0) ceramics
is negligible at less than ±0.05% versus up to ±2% for films.
Typical capacitance change with life is less than ±0.1% for C0G
(NP0), one-fifth that shown by most other dielectrics. C0G (NP0)
formulations show no aging characteristics.
PART NUMBER (see page 2 for complete part number explanation)
0805
Size
5
Voltage
A
Dielectric
101
Capacitance
Code (In pF)
J
Capacitance
Tolerance
A
Failure
Rate
A = Not
Applicable
T
Terminations
T = Plated Ni
and Sn
Contact
Factory For
1 = Pd/Ag Term
2
Packaging
A
Special
Code
A = Std.
Product
(L” x W”)
6.3V = 6
10V = Z
16V = Y
25V = 3
50V = 5
100V = 1
200V = 2
500V = 7
C0G (NP0) = A
2 Sig. Digits +
Number of Zeros
B = ±.10 pF (<10pF)
C = ±.25 pF (<10pF)
D = ±.50 pF (<10pF)
F = ±1% (≥ 10 pF)
G = ±2% (≥ 10 pF)
J = ±5%
K = ±10%
U = 4mm TR
(01005)
2 = 7” Reel
4 = 13” Reel
7 = Gold Plated
NOT RoHS
COMPLIANT
NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part
Numbers. Contact factory for non-specified capacitance values.
Contact Factory
For Multiples
4
051818
C0G (NP0) Dielectric
C0G (NP0) Dielectric
Parameter/Test
Operating Temperature Range
Range
Operating Temperature
Capacitance
Capacitance
Q
Q
Insulation Resistance
Insulation Resistance
Dielectric Strength
Parameter/Test
Specifications and Test Methods
Specifications and Test Methods
NP0 Specification Limits
-55ºC to
to +125ºC
-55ºC
+125ºC
Within specified tolerance
Within specified tolerance
<30 pF: Q≥
Q≥ 400+20 x Cap Value
<30 pF:
400+20 x Cap Value
≥30 pF: Q≥ 1000
≥30 pF: Q≥ 1000
100,000MΩ
1000MΩ - µF,
100,000MΩ or
or 1000MΩ - µF,
whichever is less
whichever is less
No breakdown or visual defects
NP0 Specification Limits
Dielectric Strength
No breakdown or visual defects
Resistance
Resistance to
to
Flexure
Flexure
Stresses
Stresses
Capacitance
Capacitance
Variation
Variation
Q
Appearance
Appearance
No defects
No defects
±5% or ±.5
±.5 pF, whichever is greater
±5% or
pF, whichever is greater
Meets Initial Values (As Above)
≥
≥ Initial Value
0.3
Initial Value x
x 0.3
Temperature Cycle Chamber
Freq.: 1.0 MHz ± 10% for
for cap ≤ 1000 pF
Freq.: 1.0 MHz ± 10%
cap ≤ 1000 pF
1.0 kHz ± 10% for cap
cap > 1000 pF
1.0 kHz ± 10% for
> 1000 pF
Voltage: 1.0Vrms ± .2V
.2V
Voltage: 1.0Vrms ±
Charge device with rated voltage for
for
Charge device with rated voltage
60 ±
± 5 secs @ room temp/humidity
60
5 secs @ room temp/humidity
Charge device with 250% of rated voltage for
for
Charge device with 250% of rated voltage
1-5 seconds, w/charge and discharge current
1-5 seconds, w/charge and discharge current
limited to
to 50 mA (max)
limited
50 mA (max)
Note: Charge device with 150% of rated
Note:
voltage for 500V
with 150% of rated
Charge device
devices.
voltage for 500V devices.
Deflection: 2mm
Deflection: 2mm
Test Time: 30 seconds
Test Time: 30 seconds
Measuring Conditions
Measuring Conditions
Temperature Cycle Chamber
Q
Meets Initial Values (As Above)
Insulation
Resistance
Resistance
Solderability
Insulation
Solderability
Appearance
Capacitance
Appearance
Variation
Q
Insulation
Resistance
Insulation
Dielectric
Resistance
Strength
Dielectric
Appearance
Strength
Capacitance
Appearance
Variation
≥ 95% of each terminal should be covered
with fresh solder
≥ 95% of each terminal should be covered
No defects, <25%
fresh solder
either end terminal
with
leaching of
No defects, <25%
±.25 pF, whichever is
terminal
≤ ±2.5% or
leaching of either end
greater
≤ ±2.5% or ±.25 pF, whichever is greater
Dip device in
for 5.0 ±
solder at 230 ± 5ºC
eutectic
0.5 seconds
for 5.0 ± 0.5 seconds
Dip device in eutectic solder at 230 ± 5ºC
Resistance to
Resistance to
Solder Heat
Solder Heat
Capacitance
Variation
Q
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Dip device in eutectic solder at 260ºC for 60
seconds. Store at room temperature for 24 ± 2
Dip device in eutectic solder at 260ºC for 60sec-
hours before measuring electrical properties.
onds. Store at room temperature for 24 ± 2hours
before measuring electrical properties.
Meets Initial Values (As Above)
No visual defects
Step 1: -55ºC ± 2º
Step 1: -55ºC ± 2º
Step 2: Room Temp
Step 2: Room Temp
Step 3: +125ºC ± 2º
30 ± 3 minutes
30 ±
3
3
minutes
≤
minutes
≤ 3 minutes
No visual defects
≤ ±2.5% or ±.25 pF, whichever is greater
≤ ±2.5% or ±.25 pF, whichever is greater
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Thermal
Shock
Thermal
Shock
Capacitance
Variation
Q
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
No visual defects
Step 3: +125ºC ± 2º
Step 4: Room Temp
30 ± 3 minutes
Q
Insulation
Resistance
Insulation
Dielectric
Resistance
Strength
Dielectric
Appearance
Strength
Capacitance
Appearance
Variation
Capacitance
30 ± 3 minutes
≤ 3 minutes
Step 4: Room Temp
≤ 3 minutes
Repeat for 5 cycles and measure after
24 hours at room
cycles and measure after
Repeat for 5
temperature
24 hours at room temperature
No visual defects
≤ ±3.0% or ± .3 pF, whichever is greater
Load Life
Load Life
(C=Nominal Cap)
Q
(C=Nominal Cap)
Variation
Q
Insulation
Resistance
Insulation
Dielectric
Resistance
Strength
Dielectric
Appearance
Strength
Capacitance
Appearance
Variation
≥10 pF, <30 pF:
Q≥ 275 +5C/2
<10 pF:
≥ Initial Value
Q≥ 200 +10C
x 0.3 (See Above)
≥ Initial Value x 0.3 (See Above)
Meets Initial
visual defects
No
Values (As Above)
≥ 30 pF:
≥10 pF, <30 pF:
≥ 30 pF:
<10 pF:
≤ ±3.0% or ± .3 pF, whichever is greater
Q≥ 350
Q≥ 275 +5C/2
Q≥ 350
Q≥ 200 +10C
Charge device with twice rated voltage in
test chamber set at 125ºC ± 2ºC
Charge device with twice rated voltage in
for 1000 hours (+48, -0).
Remove from test chamber and stabilize at
Remove
room temperature for 24 hours
at
from test chamber and stabilize
room temperature for 24 hours
before measuring.
before measuring.
test chamber set at 125ºC ± 2ºC
for 1000 hours (+48, -0).
Meets Initial Values (As Above)
≤ ±5.0% or ± .5 pF, whichever is greater
No visual defects
Q≥ 350
≤ ±5.0%
≥ 30
.5 pF, whichever is greater
or ±
pF:
≥10 pF, <30 pF:
<10
≥ 30 pF:
pF:
Q≥ 275 +5C/2
Q≥
Q≥ 350
200 +10C
≥10 pF, <30 pF:
Q≥ 275 +5C/2
≥ Initial Value x 0.3 (See Above)
<10 pF:
Q≥ 200 +10C
Load
Humidity
Load
Humidity
Capacitance
Q
Variation
Q
Insulation
Resistance
Dielectric
Insulation
Strength
Resistance
Dielectric
Strength
Meets Initial Values
Above)
≥ Initial Value x 0.3 (See
(As Above)
Meets Initial Values (As Above)
room temperature for 24 ± 2 hours
before
and stabilize
Remove from chamber
measuring.
at room
Store in a test chamber set at 85ºC ± 2ºC/
85% ± 5% relative humidity for 1000 hours
Remove
with rated voltage applied.
at
(+48, -0)
from chamber and stabilize
Store in a test chamber set at 85ºC ± 2ºC/
85% ± 5% relative humidity for 1000 hours
(+48, -0) with rated voltage applied.
temperature for 24 ± 2 hours
before measuring.
100917
051818
5
5
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
