XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
MAY 2011
REV. 1.0.0
GENERAL DESCRIPTION
The XR20M1280
1
(M1280) is a single-channel I
2
C/
SPI Universal Asynchronous Receiver and
Transmitter (UART) with integrated level shifters and
128 bytes of transmit and receive FIFOs.
For flexibility in a mixed voltage environment, the
M1280 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and I
2
C/SPI interface signals allow for the M1280 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters. The VCC pin for the core voltage helps
lower the overall power consumption of applications
that use slower data rates.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address Byte Control features increase the
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M1280 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M1280 can be minimized by
enabling the sleep mode.
The M1280 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M1280 has a selectable
I
2
C/SPI bus interface.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Integrated Level Shifters on CPU interface, UART
and GPIO signals
•
Selectable I
2
C/SPI bus interface
•
26MHz maximum SPI clock
•
24Mbps maximum UART data rate
•
Up to 16 GPIOs
•
128-Bytes TX and RX FIFOs
•
Programmable TX/RX trigger levels
•
TX/RX FIFO Level Counters
•
Independent TX/RX Baud Rate Generator
•
Fractional Baud Rate Generator
•
Auto RTS/CTS Hardware Flow Control
•
Auto XON/XOFF Software Flow Control
•
Auto RS-485 Half-Duplex Direction Control
•
Multidrop mode w/ Auto Address Detect (RX)
•
Multidrop mode w/ Address Byte Control (TX)
•
Sleep Mode with Automatic Wake-up
•
Infrared (IrDA 1.0 and 1.1) mode
•
1.62V to 3.63V supply operation
•
5V tolerant inputs
•
Crystal oscillator or external clock input
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
F
IGURE
1. XR20M1280 B
LOCK
D
IAGRAM
VCC_BUS
VCC_CORE
VCC_UART
REV. 1.0.0
SCK
SDA
A0/CS#
A1/SI
SO
IRQ#
RESET#
I2C/SPI#
EN485#
ENIR#
I
2
C/
SPI
Bus
Interface
UART
Regs
1.62V-
3.63V
I/O
Buffers
128-Byte
TX FIFO
128-Byte
RX FIFO
Flow Control
TX
RX
1.62V-
3.63V
I/O
Buffers
TX
RX
RTS#
CTS#
GPIO[3:0]
Fractional
BRG
VCC_GPIO
GPIOs
1.62V-
3.63V
I/O
Buffers
GPIO[15:4]
XTAL1
XTAL2
SLEEP/PWRDN#
Crystal Oscillator/
Buffer
ORDERING INFORMATION
P
ART
N
UMBER
XR20M1280IL24-F
XR20M1280IL24TR-F
XR20M1280IL32-F
XR20M1280IL32TR-F
XR20M1280IL40-F
XR20M1280IL40TR-F
P
ACKAGE
QFN-24
QFN-24
QFN-32
QFN-32
QFN-40
QFN-40
N
UMBER O
F
GPIO
S
4
4
8
8
16
16
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
Active
N
OTE
:
TR = Tape and reel, F = Green / RoHS
2
XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
F
IGURE
2. P
IN
O
UT
A
SSIGNMENTS
DSR#/GPIO1
DSR#/GPIO1
32
DTR#/GPIO0
DTR#/GPIO0
33
VCC_CORE
VCC_CORE
CD#/GPIO2
CD#/GPIO2
31
30
29
28
27
26
25
24
23
22
21
20
XTAL2
XTAL1
XTAL2
XTAL1
RTS#
CTS#
RTS#
35
40
39
38
37
36
35
34
33
32
31
40
39
38
37
36
VCC_BUS
I2C/SPI# 1
ENIR# 2
NC 3
SDA 4
SCL 5
IRQ# 6
A1 7
A0 8
NC 9
RESET# 10
11
XR20M1280IL40
I
2
C Mode
30
29
28
27
26
25
24
23
22
21
20
RI#/GPIO3
GND
VCC_UART
GPIO15
GPIO14
GPIO13
GPIO4
GPIO5
GPIO6
GPIO7
GND
34
CTS#
RX
RX
TX
TX
I2C/SPI# 1
ENIR# 2
SO 3
GND 4
SCL 5
IRQ# 6
SI 7
CS# 8
NC 9
RESET# 10
11
XR20M1280IL40
SPI Mode
RI#/GPIO3
GND
VCC_UART
GPIO15
GPIO14
GPIO13
GPIO4
GPIO5
GPIO6
GPIO7
12
13
14
15
16
17
18
19
12
13
14
15
16
17
GPIO10
18
GPIO11
26
CTS#
GPIO10
GPIO11
GPIO12
VCC_BUS
VCC_GPIO
VCC_BUS
GPIO12
25
DTR#/GPIO0
GPIO8
GPIO9
GPIO8
GPIO9
19
SLEEP/PWRDN#
SLEEP/PWRDN#
DTR#/GPIO0
VCC_CORE
VCC_CORE
XTAL2
XTAL1
XTAL2
XTAL1
RTS#
CTS#
32
31
30
29
28
27
26
25
32
31
30
29
28
VCC_BUS
I2C/SPI#
ENIR#
NC
SDA
SCL
IRQ#
A1
A0
1
2
3
4
5
6
7
8
XR20M1280IL32
I
2
C Mode
24
23
22
21
20
19
18
17
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
VCC_UART
GPIO4
GPIO5
GPIO6
GPIO7
GND
I2C/SPI#
ENIR#
SO
GND
SCL
IRQ#
SI
CS#
1
2
3
4
5
6
7
8
27
RTS#
RX
TX
RX
TX
VCC_GPIO
24
23
22
21
20
19
18
17
DSR#/GPIO1
CD#/GPIO2
RI#/GPIO3
VCC_UART
GPIO4
GPIO5
GPIO6
GPIO7
CD#/GPIO2
RI#/GPIO3
VCC_UART
RTS#
RX
TX
EN485#
EN485#
GND
XR20M1280IL32
SPI Mode
SLEEP/PWRDN# 10
EN485# 11
GND 12
VCC_BUS 13
NC 14
NC 15
VCC_GPIO 16
SLEEP/PWRDN# 10
GND
EN485# 11
GND 12
VCC_BUS 13
21
VCC_CORE
NC 14
20
EN485# 11
DTR#/GPIO0
DSR#/GPIO1
DTR#/GPIO0
VCC_CORE
I2C/SPI#
XTAL2
XTAL1
24
23
22
24
23
22
21
20
19
19
18
17
16
15
14
13
CTS# 12
NC
SDA
SCL
IRQ#
A1
A0
1
2
3
4
5
6
XR20M1280
IL24
2
I C Mode
VCC_BUS 10
EN485# 11
CTS# 12
7
8
9
18
17
16
15
14
13
CD#/GPIO2
RI#/GPIO3
VCC_UART
RTS#
RX
TX
SO
GND
SCL
IRQ#
SI
CS#
1
2
3
4
5
6
XR20M1280
IL24
SPI Mode
VCC_BUS 10
7
8
9
RESET#
SLEEP/PWRDN#
3
SLEEP/PWRDN#
RESET#
GND
GND
DSR#/GPIO1
VCC_BUS
GND
I2C/SPI#
XTAL2
XTAL1
NC 15
VCC_GPIO 16
9
RESET#
RESET#
9
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
N
AME
QFN-24 QFN-32
P
IN
#
PIN#
QFN-40
PIN#
T
YPE
D
ESCRIPTION
I2C (SPI) INTERFACE
I2C/SPI#
SDA
(GND)
SCL
24
2
3
1
4
5
1
4
5
I
I/O
I
I
2
C-bus or SPI interface select. I
2
C-bus interface is selected if this
pin is HIGH. SPI interface is selected if this pin is LOW
I
2
C-bus data input/output (open-drain). If SPI configuration is
selected, then this pin should be tied LOW.
I
2
C-bus or SPI serial input clock.
When the I
2
C-bus interface is selected, the serial clock idles HIGH.
When the SPI interface is selected, the serial clock idles LOW.
IRQ#
A0
(CS#)
4
6
6
8
6
8
OD
I
Interrupt output (open-drain, active LOW).
I
2
C-bus device address select A0 or SPI chip select. If I
2
C-bus con-
figuration is selected, this pin along with the A1 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI chip select pin (Schmitt-trigger, active LOW).
I
2
C-bus device address select A1 or SPI data input pin. If I
2
C-bus
configuration is selected, this pin along with A0 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI data input pin.
SPI data output pin. If I2C-bus configuration is selected, this pin
must be left unconnected.
Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will
reset the internal registers and all outputs. The UART transmitter
output will be idle and the receiver input will be ignored.
A1
(SI)
5
7
7
I
SO
(NC)
RESET#
1
7
3
9
3
10
O
I
MODEM I/O and GPIOs
TX
13
28
36
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
UART Request-to-Send (active low) or general purpose output. This
output must be asserted prior to using auto RTS flow control, see
EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
General purpose I/O or UART Data-Terminal-Ready (active low).
General purpose I/O or UART Data-Set-Ready (active low).
RX
14
29
37
I
RTS#
15
27
35
O
CTS#
12
26
34
I
GPIO0/DTR#
GPIO1/DSR#
20
19
25
24
33
32
I/O
I/O
4
XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
N
AME
GPIO2/CD#
GPIO3/RI#
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
QFN-24 QFN-32
P
IN
#
PIN#
18
17
-
-
-
-
-
-
-
-
-
-
-
-
23
22
20
19
18
17
-
-
-
-
-
-
-
-
QFN-40
PIN#
31
30
24
23
22
21
15
16
17
18
19
25
26
27
T
YPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D
ESCRIPTION
General purpose I/O or UART Carrier-Detect (active low).
General purpose I/O or UART Ring-Indicator (active low).
General purpose I/Os.
General purpose I/Os.
ANCILLARY SIGNALS
XTAL1
XTAL2
EN485#
22
23
11
31
32
11
39
40
12
I
O
I
Crystal or external clock input. Note: This input is not 5V tolerant.
Crystal or buffered clock output.
Enable Auto RS-485 Half-Duplex Mode. This pin is sampled upon
power-up. If this pin is HIGH, then the RTS# output can be used for
Auto RTS Hardware Flow Control or as a general purpose output. If
this pin is LOW, then the RTS# output is the Auto RS-485 Half-
Duplex direction control pin.
Enable IR Mode. This pin is sampled upon power-up. If this pin is
HIGH, then the TX output and RX input will behave as the UART
transmit data output and UART receive data input. If this pin is
LOW, then the TX output and RX input will behave as the infrared
encoder data output and the infrared receive data input.
Sleep / Power Down pin. This pin powers up as the SLEEP input.
The SLEEP input can force the UART to enter into the sleep mode
after the next byte transmitted or received without meeting any of
the sleep mode conditions.
This pin can also be configured as an output pin which can be used
to indicate to the CPU that the UART has entered the sleep mode.
This output can also be used to power down other devices.
1.62V to 3.63V VCC for the core. This supply voltage is used for the
core logic including the crystal oscillator circuit.
1.62V to 3.63V VCC for bus interface signals.
This supply voltage pin will determine the I/O levels of the CPU bus
interface signals.
1.62V to 3.63V VCC for the UART signals.
This supply voltage pin will determine the I/O levels of the UART I/O
signals including GPIO[3:0].
ENIR#
-
2
2
I
SLEEP/
PWRDN#
8
10
11
I/O
VCC_CORE
VCC_BUS
21
10
30
13
38
14
Pwr
Pwr
VCC_UART
16
21
28
Pwr
5
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