74LV03D,118 datasheet, PDF - EEWORLD Datasheet

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74LV03D,118: DescriptionIC GATE NAND 4CH 2-INP 14SO; Categorylogic logic; File Size164KB，12 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74LV03D,118 Overview

IC GATE NAND 4CH 2-INP 14SO

74LV03D,118 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	SOIC
package instruction	SOP,
Contacts	14
Manufacturer packaging code	SOT108-1
Reach Compliance Code	compliant
Factory Lead Time	4 weeks
Samacsys Description	74LV03 - Quad 2-input NAND gate@en-us
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	8.65 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	31 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
Base Number Matches	1

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74LV03

Quad 2-input NAND gate

Rev. 4 — 31 August 2017

Product data sheet

General description

The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible

with 74HC/HCT03.

The 74LV03 provides the 2-input NAND function.

The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode

connected to V

. In the OFF-state, i.e., when one input is LOW, the output may be

pulled to any voltage between GND and V

O(max)

. This allows the device to be used as

a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output

applications, these devices must have a pull-up resistor to establish a logic HIGH level.

Features and benefits

•

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical V

OLP

(output ground bounce) < 0.8 V @ V

= 3.3 V, T

amb

= 25 °C

Typical V

OHV

(output V

undershoot) > 2 V @ V

= 3.3 V, T

amb

= 25 °C

Level shifter capability

ESD protection:

–

HBM JESD22-A114F exceeds 2000 V

–

MM JESD22-A115-A exceeds 200 V

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Ordering information

Package

Temperature range

Name

SO14

Table 1. Ordering information

Type number

74LV03D

Description

plastic small outline package; 14 leads;

body width 3.9 mm

Version

SOT108-1

-40 °C to + 125 °C

74LV03D,118 Related Products

	74LV03D,118	74LV03D,112
Description	IC GATE NAND 4CH 2-INP 14SO	IC GATE NAND 4CH 2-INP 14SO
Brand Name	Nexperia	Nexperia
Maker	Nexperia	Nexperia
Parts packaging code	SOIC	SOIC
package instruction	SOP,	SOP-14
Contacts	14	14
Manufacturer packaging code	SOT108-1	SOT108-1
Reach Compliance Code	compliant	compliant
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4
length	8.65 mm	8.65 mm
Logic integrated circuit type	NAND GATE	NAND GATE
Humidity sensitivity level	1	1
Number of functions	4	4
Number of entries	2	2
Number of terminals	14	14
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	OPEN-DRAIN	OPEN-DRAIN
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260
propagation delay (tpd)	31 ns	31 ns
Maximum seat height	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1 V	1 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	3.9 mm	3.9 mm
Base Number Matches	1	1

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