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Spartan-3 FPGA Family:
Complete Data Sheet
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DS099 January 17, 2005
This document includes all four modules of the Spartan™-3 FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS099-1 (v1.4) January 17, 2005
6 pages
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•
•
•
•
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Introduction
Features
Architectural Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS099-3 (v1.5) December 17, 2004
39 pages
•
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- Internal Logic Timing
- DCM Timing
- Configuration and JTAG Timing
•
Module 2:
Functional Description
DS099-2 (v1.3) August 24, 2004
40 pages
•
IOBs
- IOB Overview
- SelectIO™ Signal Standards
CLB Overview
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
- Clock Network
Configuration
Module 4:
Pinout Descriptions
DS099-4 (v1.6) January 17, 2005
112 pages
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Pin Descriptions
- Pin Behavior During Configuration
Package Overview
Pinout Tables
- Footprints
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IMPORTANT NOTE:
The Spartan-3 FPGA data sheet is created and published in separate modules. This complete version
is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for
each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in
this volume.
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099 January 17, 2005
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Spartan-3 FPGA Family:
Introduction and Ordering
Information
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DS099-1 (v1.4) January 17, 2005
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Preliminary Product Specification
Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
SelectIO™ signaling
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 6 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE development system
- Synthesis, mapping, placement and routing
MicroBlaze™ processor, PCI, and other cores
Pb-free packaging options
Low-power Spartan-3L Family and Automotive
Spartan-3 XA Family options
Maximum
Differential
I/O Pairs
56
76
116
175
221
270
312
344
Introduction
The Spartan™-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in
Table 1.
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from state-of-the-art Virtex™-II tech-
nology. These Spartan-3 enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
•
-
•
•
•
•
•
•
•
•
Features
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
Table 1:
Summary of Spartan-3 FPGA Attributes
System Equivalent
Gates Logic Cells Rows Columns Total CLBs
50K
200K
400K
1M
1.5M
2M
4M
5M
1,728
4,320
8,064
17,280
29,952
46,080
62,208
74,880
16
24
32
48
64
80
96
104
12
20
28
40
52
64
72
80
192
480
896
1,920
3,328
5,120
6,912
8,320
CLB Array
(One CLB = Four Slices)
•
Device
XC3S50
2
XC3S200
2
XC3S400
2
XC3S1000
2, 3
XC3S1500
3
XC3S2000
XC3S4000
3
XC3S5000
Distributed
RAM (bits
1
)
12K
30K
56K
120K
208K
320K
432K
520K
Block RAM
(bits
1
)
72K
216K
288K
432K
576K
720K
1,728K
1,872K
Dedicated
Multipliers
4
12
16
24
32
40
96
104
DCMs
2
4
4
4
4
4
4
4
Maximum
User I/O
124
173
264
391
487
565
712
784
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
2. These devices are available in Xilinx Automotive versions as described in
DS314:
Spartan-3 Automotive XA FPGA Family.
3. XC3S1000, XC3S1500, and XC3S4000 are also available in lower static power versions as described in
DS313:
Spartan-3L Low Power FPGA Family.
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v1.4) January 17, 2005
Preliminary Product Specification
www.xilinx.com
1
Spartan-3 FPGA Family: Introduction and Ordering Information
R
Architectural Overview
The Spartan-3 family architecture consists of five funda-
mental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-four different signal
standards,
including
seven
high-performance
differential standards, are available as shown in
Table 2.
Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI)
feature provides automatic on-chip terminations,
simplifying board designs.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
•
•
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
•
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. The XC3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XC3S200 to the XC3S2000
have two columns of block RAM. The XC3S4000 and
XC3S5000 devices have four RAM columns. Each column
is made up of several 18K-bit RAM blocks; each block is
associated with a dedicated multiplier. The DCMs are posi-
tioned at the ends of the outer block RAM columns.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple con-
nections to the routing.
•
DS099-1_01_032703
Notes:
1. The two additional block RAM columns of the XC3S4000 and XC3S5000
devices are shown with dashed lines. The XC3S50 has only the block RAM
column on the far left.
Figure 1:
Spartan-3 Family Architecture
2
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DS099-1 (v1.4) January 17, 2005
Preliminary Product Specification
R
Spartan-3 FPGA Family: Introduction and Ordering Information
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before pow-
ering on the FPGA, configuration data is stored externally in
a PROM or some other nonvolatile medium either on or off
the board. After applying power, the configuration data is
written to the FPGA using any of five different modes: Mas-
ter Parallel, Slave Parallel, Master Serial, Slave Serial, and
Boundary Scan (JTAG). The Master and Slave Parallel
modes use an 8-bit wide SelectMAP™ port.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
Standard
Category
Single-Ended
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 6 differential standards as listed in
Table 2.
Many standards support the DCI feature, which
uses integrated terminations to eliminate unwanted signal
reflections.
Table 3
shows the number of user I/Os as well
as the number of differential I/O pairs available for each
device/package combination.
Table 2:
Signal Standards Supported by the Spartan-3 Family
Description
Gunning Transceiver Logic
High-Speed Transceiver Logic
V
CCO
(V)
N/A
1.5
1.8
Class
Terminated
Plus
HSTL
I
III
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
LVTTL
PCI
SSTL
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
3.3
3.0
1.8
2.5
Differential
Symbol
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
DCI
Option
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Yes
GTL
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
N/A (±6.7 mA)
N/A (±13.4 mA)
I
II
LDT
(ULVDS)
LVDS
Lightning Data Transport
(HyperTransport™)
Low-Voltage Differential Signaling
2.5
N/A
Standard
Bus
Extended Mode
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
No
Yes
No
Yes
No
No
LVPECL
RSDS
Low-Voltage Positive Emitter-Coupled
Logic
Reduced-Swing Differential Signaling
2.5
2.5
N/A
N/A
DS099-1 (v1.4) January 17, 2005
Preliminary Product Specification
www.xilinx.com
3
Spartan-3 FPGA Family: Introduction and Ordering Information
Table 3:
Spartan-3 I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
User
63
63
-
-
-
-
-
-
Diff
29
29
-
-
-
-
-
-
CP132
CPG132
User
89
-
-
-
-
-
-
-
Diff
44
-
-
-
-
-
-
-
TQ144
TQG144
User
97
97
97
-
-
-
-
-
Diff
46
46
46
-
-
-
-
-
PQ208
PQG208
User
124
141
141
-
-
-
-
-
Diff
56
62
62
-
-
-
-
-
FT256
FTG256
User
-
173
173
173
-
-
-
-
Diff
-
76
76
76
-
-
-
-
FG320
FGG320
User
-
-
221
221
221
-
-
-
Diff
-
-
100
100
100
-
-
-
FG456
FGG456
User
-
-
264
333
333
333
-
-
Diff
-
-
116
149
149
149
-
-
FG676
FGG676
User
-
-
-
391
487
489
489
-
Diff
-
-
-
175
221
221
221
-
FG900
FGG900
User
-
-
-
-
-
565
633
633
Diff
-
-
-
-
-
270
300
300
FG1156
FGG1156
User
-
-
-
-
-
-
712
784
Diff
-
-
-
-
-
-
312
344
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Notes:
1. All device options listed in a given package column are pin-compatible.
2. User = User I/O pins. Diff = Differential I/O pairs.
Package Marking
Mask Revision Code
Fabrication Code
F = UMC 8D (200 mm)
G = UMC 12A (300 mm)
R
R
Device Type
Package
Speed Grade
Temperature Range
SPARTAN
XC3S50
TM
PQ208AFQ0350
xxxxxxxxx
4C
Process Technology
Q = 90 nm
Date Code
Lot Code
ds099-1_03_011705
4
6
www.xilinx.com
DS099-1 (v1.4) January 17, 2005
Preliminary Product Specification
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