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XC3S100E-5VQ100GC

Description
FPGA, 240 CLBS, 100000 GATES, 572 MHz, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size3MB,231 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XC3S100E-5VQ100GC Overview

FPGA, 240 CLBS, 100000 GATES, 572 MHz, PQFP100

XC3S100E-5VQ100GC Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals100
Maximum supply/operating voltage1.26 V
Minimum supply/operating voltage1.14 V
Rated supply voltage1.2 V
Processing package description16 × 16 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeFLATPACK, THIN PROFILE, FINE PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.5000 mm
terminal coatingtin lead
Terminal locationFour
Packaging MaterialsPlastic/Epoxy
organize240 CLBS, 100,000 doors
Maximum FCLK clock frequency572 MHz
Number of configurable logic modules240
Programmable logic typeFIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits100000
The maximum delay of a CLB module0.7600 ns
0
R
Spartan-3E FPGA Family:
Complete Data Sheet
0
0
DS312 November 9, 2006
Product Specification
Module 1:
Introduction and Ordering Information
DS312-1 (v3.4) November 9, 2006
Introduction
Features
Architectural Overview
Package Marking
Ordering Information
Module 3:
DC and Switching Characteristics
DS312-3 (v3.4) November 9, 2006
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- SLICE Timing
- DCM Timing
- Block RAM Timing
- Multiplier Timing
- Configuration and JTAG Timing
Module 2:
Functional Description
DS312-2 (v3.4) November 9, 2006
Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
Configurable Logic Block (CLB)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Powering Spartan-3E FPGAs
Production Stepping
Module 4:
Pinout Descriptions
DS312-4 (v3.4) November 9, 2006
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
© 2005-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 November 9, 2006
www.xilinx.com
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