DATASHEET
ISL62881C, ISL62881D
Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs
The ISL62881C provides a complete solution for
microprocessor and graphic processor core power
supply with it’s integrated gate drive. Based on
Intersil’s Robust Ripple regulator (R3™) technology,
the PWM modulator compared to traditional
modulators, has faster transient settling time, variable
switching frequency during load transients and has
improved light load efficiency with its ability to
automatically change switching frequency.
Fully compliant with IMVP6.5™, the ISL62881C is
easily configurable as a CPU or graphics V
CORE
controllers by offering: responds to DPRSLPVR signals
by entering/exiting diode emulations mode; reports
regulator output current via the IMON pin; senses
current by using a discrete resistor or the inductor;
over-temperature thermal compensation of DCR, using
a single NTC thermistor; differential sensing to
accurately monitor and adjust processor die voltage;
minimizes body diode conduction loss in diode
emulation mode with it’s adaptive body diode
conduction time.
Need to aggressively reduce the output capacitor? The
overshoot reduction function is user-selectable and can
be disabled for those concerned about increased
system thermal stress.
Maintaining all the ISL62881C functions, the
ISL62881D offers VR_TT# function for thermal
throttling control. It also offers the split LGATE function
to further improve light load efficiency.
FN7596
Rev 0.00
March 8, 2010
Features
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Current Monitor
• Differential Remote Voltage Sensing
• Integrated Gate Driver
• Split LGATE Driver to Increase Light-Load
Efficiency (For ISL62881D)
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 28 Ld 4x4 or 32 Ld 5x5 TQFN
Package
Applications
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
Related Literature
• See
AN1552
for Evaluation Board Application Note
“ISL62881CCPUEVAL2Z User Guide”
• See
AN1553
for Evaluation Board Application Note
“ISL62881CGPUEVAL2Z User Guide”
Load Line Regulation
0.91
0.90
0.89
0.88
V
OUT
(V)
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
0
2
4
6
8
10 12 14
I
OUT
(A)
V
IN
= 12V
V
IN
= 8V
16
18
20
22
V
IN
= 19V
FN7596 Rev 0.00
March 8, 2010
Page 1 of 37
ISL62881C, ISL62881D
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL62881CHRTZ
ISL62881CIRTZ
ISL62881DHRTZ
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL62881C, ISL62881D.
For more information on
MSL please see techbrief
TB363.
PART MARKING
62881C HRTZ
62881C IRTZ
62881D HRTZ
TEMP. RANGE
(°C)
-10 to +100
-40 to +100
-10 to +100
PACKAGE
(Pb-Free)
28 Ld 4x4 TQFN
28 Ld 4x4 TQFN
32 Ld 5x5 TQFN
PKG.
DWG. #
L28.4x4
L28.4x4
L32.5x5E
Pin Configurations
ISL62881C
(28 LD TQFN)
TOP VIEW
DPRSLPVR
CLK_EN#
DPRSLPVR
VR_ON
ISL62881D
(32 LD TQFN)
TOP VIEW
VR_ON
VID3
VID4
VID6
VID5
VID2
VID6
VID5
VID3
VID4
28 27 26 25 24 23 22
CLK_EN# 1
PGOOD 2
RBIAS 3
VW
4
GND PAD
(BOTTOM)
21 VID1
20 VID0
19 VCCP
18 LGATE
17 VSSP
16 PHASE
15 UGATE
8
RTN
32 31 30 29 28 27 26 25
PGOOD 1
RBIAS 2
VR_TT# 3
NTC 4
GND 5
VW 6
COMP 7
FB 8
9 10 11 12 13 14 15 16
VIN
ISUM-
ISUM+
IMON
BOOT
VSEN
RTN
VDD
VID2
24 VID1
23 VID0
22 VCCP
GND PAD
(BOTTOM)
21 LGATEb
20 LGATEa
19 VSSP
18 PHASE
17 UGATE
COMP 5
FB
6
VSEN 7
9
ISUM-
10 11 12 13 14
VIN
IMON
ISUM+
BOOT
VDD
Pin Function Description
ISL62881C ISL62881D
1
2
3
32
1
2
SYMBOL
CLK_EN#
PGOOD
RBIAS
DESCRIPTION
Open drain output to enable system PLL clock. It goes low 13 switching cycles after
V
CORE
is within 10% of V
BOOT
.
Power-Good open-drain output indicating when the regulator is able to supply
regulated voltage. Pull up externally with a 680 resistor to VCCP or 1.9k to 3.3V.
A resistor to GND sets internal current reference. A 147k resistor sets the controller
for CPU core application and a 47k resistor sets the controller for GPU core
application.
Thermal overload output indicator.
Thermistor input to VR_TT# circuit.
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND
pin.
-
-
-
3
4
5
VR_TT#
NTC
GND
FN7596 Rev 0.00
March 8, 2010
Page 2 of 37
ISL62881C, ISL62881D
Pin Function Description
(Continued)
ISL62881C ISL62881D
4
5
6
7
8
9, 10
11
12
13
14
6
7
8
9
10
11, 12
13
14
15
16
SYMBOL
VW
COMP
FB
VSEN
RTN
ISUM- and
ISUM+
VDD
VIN
IMON
BOOT
DESCRIPTION
A resistor from this pin to COMP programs the switching frequency (8k gives
approximately 300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND
adjusts the overcurrent threshold.
This pin is the inverting input of the error amplifier.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
5V bias power.
Power stage supply voltage, used for feed-forward.
An analog output. IMON outputs a current proportional to the regulator output
current.
Connect an MLCC capacitor across the BOOT and the PHASE pin. The boot capacitor
is charged through an internal boot diode connected from the VCCP pin to the BOOT
pin, each time the PHASE pin drops below VCCP minus the voltage dropped across the
internal boot diode.
Output of the high-side MOSFET gate driver. Connect the UGATE pin to the gate of the
high-side MOSFET.
Current return path for the high-side MOSFET gate driver. Connect the PHASE pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and
the output inductor.
Current return path for the low-side MOSFET gate driver. Connect the VSSP pin to the
source of the low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE pins to the gates of the low-side MOSFET.
Output of the low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
Output of the low-side MOSFET gate driver that is always active. Connect the LGATEa
pin to the gate of the low-side MOSFET that is active all the time.
Another output of the low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATEb pin to the gate of the
low-side MOSFET that is idle in deeper sleep mode.
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin.
Decouple with at least 1µF of an MLCC capacitor to the VSSP pin.
15
16
17
18
UGATE
PHASE
17
19
VSSP
18
-
-
-
20
21
LGATE
LGATEa
LGATEb
19
20, 21, 22,
23, 24, 25,
26
22
23, 24, 25,
26, 27, 28
29
VCCP
VID input with VID0 = LSB and VID6 = MSB.
VID0,
VID1,
VID2,
VID3,
VID4,
VID5, VID6
VR_ON
DPRSLPVR
BOTTOM
Voltage regulator enable input. A high level logic signal on this pin enables the
regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the
microprocessor is in deeper sleep mode.
The bottom pad is electrically connected to the GND pin inside the IC. It should also
be used as the thermal pad for heat removal.
27
28
pad
30
31
FN7596 Rev 0.00
March 8, 2010
Page 3 of 37
ISL62881C, ISL62881D
Block Diagram
VIN VSEN
PGOOD CLK_EN#
VDD
VR_ON
MODE
CONTROL
DPRSLPVR
RBIAS
PROTECTION
VID0
VID1
VID2
VID3
VID4
VID5
DAC
AND
SOFT
START
VIN
WOC OC
CLOCK
VDAC
COMP
VW
PGOOD
AND
CLK_EN#
LOGIC
FLT
6µA 54µA 1.20V
1.24V
VR_TT#
NTC
ISL62881D
ONLY
PWM CONTROL LOGIC
VID6
RTN
FB
COMP
VW
Idroop
Imon
IMON
ISUM+
ISUM-
CURRENT
SENSE
2.5
X
WOC
VIN
VDAC
BOOT
DRIVER
UGATE
PHASE
E/A
SHOOT
THROUGH
PROTECTION
DRIVER
VCCP
LGATEA
VSSP
ISL62881C ONLY
MODULATOR
COMP
CURRENT
60µA
COMPARATORS
OC
DRIVER
LGATEB
ISL62881D
ONLY
GND
ADJ. OCP
THRESHOLD
COMP
FN7596 Rev 0.00
March 8, 2010
Page 4 of 37
ISL62881C, ISL62881D
Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . .
Load Line Regulation . . . . . . . . . . . . . . . . . . . .
Pin Function Description . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . .
Thermal Information . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . .
Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . .
Gate Driver Timing Diagram. . . . . . . . . . . . . . .
Simplified Application Circuits . . . . . . . . . . . . .
Theory of Operation . . . . . . . . . . . . . . . . . . . .
1
1
2
4
6
6
6
6
9
9
12
Key Component Selection . . . . . . . . . . . . . . . . 18
R
BIAS
...........................................................
Inductor DCR Current-Sensing Network ............
Resistor Current-Sensing Network ..................
Overcurrent Protection ...................................
Load Line Slope.............................................
Current Monitor.............................................
Compensator ................................................
Optional Slew Rate Compensation Circuit
for 1-Tick VID Transition ...............................
Voltage Regulator Thermal Throttling ...............
18
18
20
21
21
21
22
24
24
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . 25
CPU Application Reference Design
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . 29
GPU Application Reference Design
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . 30
Typical Performance . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . 35
Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing
L28.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Outline Drawing
L32.5x5E
.
Multiphase R3™ Modulator .............................. 12
Diode Emulation and Period Stretching.............. 13
Start-up Timing ............................................. 13
Voltage Regulation and Load Line
Implementation ........................................... 14
Differential Sensing ........................................ 16
CCM Switching Frequency ............................... 16
Modes of Operation ........................................16
Dynamic Operation......................................... 16
Protections .................................................... 17
Current Monitor ............................................. 17
Adaptive Body Diode Conduction
Time Reduction ............................................ 18
Overshoot Reduction Function.......................... 18
............................
37
FN7596 Rev 0.00
March 8, 2010
Page 5 of 37
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