This X76F641 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
64K
X76F641
Secure Serial Flash
DESCRIPTION
8Kx8 + 32x8
FEATURES
•64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
•8192 Byte+32 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
•Programmable Passwords
•Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
•32-bit Response to Reset (RST Input)
•32 byte Sector Program
•400kHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
—2.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
•High Reliability Endurance:
—100,000 Write Cycles
•Data Retention: 100 years
•Available in:
—8 lead EIAJ SOIC
—SmartCard Module
The X76F641 is a Password Access Security Supervisor,
containing one 65536-bit Secure Serial Flash array and
one 256-bit Secure Serial Flash array. Access to each
memory array is controlled by five 64-bit passwords
each. These passwords protect read and write opera-
tions of the memory array. A separate RESET password
is used to reset the passwords and clear the memory
arrays in the event the read and write passwords are lost.
The X76F641 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
The X76F641 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F641 utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
TM
cell,
Functional Diagram
SCL
SDA
INTERFACE
LOGIC
DATA TRANSFER
ARRAY ACCESS
ENABLE
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RST
RESET
RESPONSE REGISTER
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
∧Xicor,
Inc. 1994, 1995, 1996 Patents
Pending 9900-5004.5 3/9/99 EP
1
Characteristics subject to change without notice
X76F641
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. During
a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all
other cases, this pin is in a high impedance state.
PIN NAMES
Symbol
SDA
SCL
RST
Vcc
Vss
NC
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
Reset (RST)
RST is a device reset pin. When RST is pulsed high the
PIN CONFIGURATION
X76F641 will output 32 bits of fixed data which conforms
to the standard for “synchronous response to reset”. part
The
must not be in a write cycle for the response to reset to
occur. See Figure 11. If there is power interrupted dur-
EIAJ SOIC
ing the Response to Reset, the response to reset will be
aborted and the part will return to the standby state. The
V
SS
V
CC
1
8
response to reset is "mask programmable" only!
NC
2
3
4
7
6
5
RST
SCL
NC
V
CC
RST
SCL
Smart Card
DEVICE OPERATION
There are two primary modes of operation for
the X76F641; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
SDA
NC
GND
NC
SDA
The basic method of communication for the device is
generating a start condition, then transmitting a com-
NC
NC
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
7025 FM 02
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
After each transaction is completed, the X76F641 will
(see Acknowledge Polling.) Only after the correct pass-
reset and enter into a standby mode. This will also be the
word is accepted and a ACK polling has been performed,
response if an unsuccessful attempt is made to access a
can the data transfer occur.
protected array.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer being
followed by an ACK, generated by the receiving
device.
If the X76F641 is in a nonvolatile write cycle a “no A
CK”
(SDA=High) response will be issued in response to loading
of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be terminated
and the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
2
X76F641
Figure 1. X76F641 Device Operation
LOAD COMMAND BYTE
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F641 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts are
inhibited while a write is in progress.
Stop Condition
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
LOAD 2 BYTE ADDRESS
READ/WRITE
DATA BYTES
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used to
reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
Acknowledge
7025 FM 03
Twc OR DATA ACK POLLING
Retry Counter
The X76F641 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is The X76F641 will respond with an acknowledge after
locked by preventing any read or write array password recognition of a start condition and its slave address. If
matches. The passwords are unaffected. If a correct both the device and a write condition have been
selected, the X76F641 will respond with an acknowledge
password is received prior to retry counter overflow, the
after the receipt of each subsequent eight-bit word.
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
Reset Device Command
command must be used with a RESET password.
The reset device command is used to clear the retry
counter and reactivate the device. When the reset device
Device Protocol
The X76F641 supports a bidirectional bus oriented proto- command is used prior to the retry counter overflow, the retry
col. The protocol defines any device that sends data onto counter is reset and no arrays or passwords are
the bus as a transmitter and the receiving device as aaffected. If the retry counter has overflowed, all memory
areas are cleared and all commands are blocked and the
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master willretry counter is disabled. Issuing a valid reset device
command (with reset password) to the device resets and
always initiate data transfers and provide the clock for
re-enables the retry counter and re-enables the other
both transmit and receive operations. Therefore, the
commands. Again, the passwords are not affected.
X76F641 will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
3
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
Reset Password Command
A reset password command will clear both arrays and set all
passwords to all zero.
X76F641
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
7025 FM 04
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
7025 FM 05
Table 1. X76F641 Instruction Set
1st Byte
after Start
1000 0000
1000 1000
1001 0000
1001 1000
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
1st Byte
after
Password
High Address
High Address
High Address
High Address
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
not used
not used
All the rest
2nd Byte
after
Password
Low address
Low address
Low address
Low address
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
not used
not used
Command Description
Read (Array 0)
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Reset Password Command
Reset Device Command
ACK Polling command (Ends Password operation)
Reserved
Password
used
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Reset
Reset
None
7025 FM T04
Notes:Illegal
command codes will be disregarded. The part will respond with a “no-A to the illegal byte and then return to the standby mode.
CK”
All write/read operations require a password.
4
X76F641
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack
command, the address and then the data bytes trans-
ferred as illustrated in figure 4. Up to 32 bytes may be
transferred. After the last byte to be transferred is
acknowledged a stop condition is issued which starts the
nonvolatile write cycle.
Figure 4. Sector Programming
START
COMMAND
Write
Password
7
Write
Password
0
SDA S
ACK
ACK
ACK
ACK
Wait t
WC
OR
Repeated
ACK Polling
Command
If ACK, Then
Password Matches
START
ACK POLLING
COMMAND
A15
A14
A13
A12
A11
A10
Data 0
S
ACK
ACK
NACK
ACK
ACK
S
ACK
ACK
Wait t
WC
Data
ACK Polling
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
...
Data 31
STOP
7025 FM 07
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