®
X40420, X40421
4kbit EEPROM
Data Sheet
May 25, 2006
FN8117.1
PRELIMINARY
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—V
TRIP2
programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor two voltages or detect power fail
• Battery switch backup
• V
OUT
: 5mA to 50mA from V
CC
; or 250µA from
V
BATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14 Ld SOIC, TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
V2MON
•
•
•
•
Monitor voltages: 5V to 1.6V
Memory security
Battery switch backup
V
OUT
5mA to 50mA
APPLICATIONS
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
X40420, X40421
Standard V
TRIP1
Level
4.6V (±1%)
4.6V (±1%)
2.9V(±1.7%)
Standard V
TRIP2
Level
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
Suffix
-A
-B
-C
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
Lock
™
protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
+
V2 Monitor
Logic
-
V
OUT
V
TRIP2
V2FAIL
SDA
WP
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
EEPROM
Array
V
OUT
Watchdog
and
Reset Logic
V
OUT
WDO
MR
RESET
X40420
RESET
X40421
SCL
V
CC
(V1MON)
+
V
CC
Monitor
Logic
-
V
TRIP1
Power-on,
Manual Reset
Low Voltage
Reset
Generation
BATT-ON
V
OUT
V
BATT
System
Battery
Switch
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40420, X40421
Ordering Information
PART
NUMBER*
WITH RESET
X40420S14-C
X40420S14I-C
X40420V14-C
X40420V14I-C
X40420S14-B
PART
MARKING
X40420S C
X40420S IC
X4042 0VC
X4042 0VIC
X40420S B
PART
NUMBER*
WITH RESET
X40421S14-C
PART
MARKING
X40421S C
MONITORED
V
CC
SUPPLIES
1.6 to 3.6
V
TRIP1
RANGE
V
TRIP2
RANGE
TEMP.
RANGE (°C)
0 to 70
-40 to +85
0 to 70
-40 to +85
2.6 to 5.5
4.6V ±50mV 2.6V ±50mV
0 to 70
0 to 70
PACKAGE
14 Ld SOIC
(150 mil)
14 Ld SOIC
(150 mil)
PKG.
DWG. #
MDP0027
MDP0027
2.9V ±50mV 1.6V ±50mV
X40421S14I-C X40421S IC
X40421V14-C
X40421V C
14 Ld TSSOP M14.173
(4.4mm)
14 Ld TSSOP M14.173
(4.4mm)
14 Ld SOIC
(150 mil)
14 Ld SOIC
(150 mil)
(Pb-free)
14 Ld SOIC
(150 mil)
14 Ld SOIC
(150 mil)
(Pb-free)
MDP0027
MDP0027
X40421V14I-C X40421V IC
X40421S14-B
X40421S B
X40420S14Z-B X40420S ZB X40421S14Z-B X40421S ZB
(Note)
(Note)
X40420S14I-B
X40420S IB
X40421S14I-B
X40421S IB
-40 to +85
-40 to +85
MDP0027
MDP0027
X40420S14IZ-B X40420S ZIB X40421S14IZ-B X40421S ZIB
(Note)
(Note)
X40420V14-B
X4042 0VB
X40421V14-B
X40421V B
0 to 70
0 to 70
14 Ld TSSOP M14.173
(4.4mm)
14 Ld TSSOP M14.173
(4.4mm)
(Pb-free)
14 Ld TSSOP M14.173
(4.4mm)
14 Ld TSSOP M14.173
(4.4mm)
(Pb-free)
14 Ld SOIC
(150 mil)
14 Ld SOIC
(150 mil)
(Pb-free)
14 Ld SOIC
(150 mil)
14 Ld SOIC
(150 mil)
(Pb-free)
MDP0027
MDP0027
X40420V14Z-B X4042 0VZB X40421V14Z-B X40421V ZB
(Note)
(Note)
X40420V14I-B
X4042 0VIB
X40421V14I-B
X40421V IB
-40 to +85
-40 to +85
X40420V14IZ-B X4042 0VZIB X40421V14IZ-B X40421V ZIB
(Note)
(Note)
X40420S14-A
X40420S A
X40421S14-A
X40421S A
2.9 to 5.5
2.9V ±50mV
0 to 70
0 to 70
X40420S14Z-A X40420S ZA X40421S14Z-A X40421S ZA
(Note)
(Note)
X40420S14I-A
X40420S IA
X40421S14I-A
X40421S IA
-40 to +85
-40 to +85
MDP0027
MDP0027
X40420S14IZ-A X40420S ZIA X40421S14IZ-A X40421S ZIA
(Note)
(Note)
X40420V14Z-A X4042 0VZA X40421V14Z-A X40421V ZA
(Note)
(Note)
X40420V14-A
X40420V14I-A
X4042 0VA
X4042 0VIA
X40421V14-A
X40421V14I-A
X40421V A
X40421V IA
0 to 70
14 Ld TSSOP M14.173
(4.4mm)
(Pb-free)
14 Ld TSSOP M14.173
(4.4mm)
14 Ld TSSOP M14.173
(4.4mm)
14 Ld TSSOP M14.173
(4.4mm)
(Pb-free)
0 to 70
-40 to +85
-40 to +85
X40420V14IZ-A X4042 0VZIA X40421V14IZ-A X40421V ZIA
(Note)
(Note)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
May 25, 2006
X40420, X40421
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
TRIP1
point.
RESET/RESET is active until V
CC
returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V
CC
with V
BATT
input
and connects V
OUT
to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40420, X40421 can
drive 50mA from V
CC
to 250µA from V
BATT
. The
device only switches to V
BATT
when V
CC
drops below
the low V
CC
voltage threshold and V
BATT
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
PIN CONFIGURATION
X40420
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
BATT-ON
V
OUT
V
BATT
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V
SS
X40421
14-Pin SOIC, TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
BATT-ON
V
OUT
V
BATT
WP
SCL
SDA
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Example Application
Unreg.
Supply
5V
REG
BATT-ON
V
CC
+
V
BATT
V
OUT
Enable
SRAM
Addr
Addr
uC
NMI
V
CC
IRQ
RESET
Manual
Reset
I
2
C
X40420, X40421
V2MON
V2FAIL
VDO
RESET
MR
SCL SDA
PIN DESCRIPTION
Pin
1
2
Name
V2FAIL
V2MON
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when
not used.
Early Low V
CC
Detect.
This open drain output signal goes LOW when
V
CC
< V
TRIP1
.
When
V
CC
> V
TRIP1
, this pin is pulled high with the use of an external pull up resistor.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain
HIGH/LOW until the pin is released and for the t
PURST
thereafter. It has an internal pull up resistor.
3
4
5
LOWLINE
WDO
MR
3
May 25, 2006
X40420, X40421
PIN DESCRIPTION
(Continued)
Pin
6
Name
RESET/
RESET
Function
RESET Output.
(X40421) This open drain pin is an active LOW output which goes LOW whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
RESET Output.
(X40420) This pin is an active HIGH open drain output which goes HIGH whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10MΩ typical)
Battery Supply Voltage.
This input provides a backup supply in the event of a failure of the
primary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not
used, connect V
BATT
to ground.
Output Voltage. (V)
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
then V
OUT
= V
CC
if V
CC
> V
BATT
+ 0.03V
else V
OUT
= V
BATT
(ie if V
CC
< V
BATT
- 0.03V)
Note:
There is hysteresis around V
BATT
± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to V
OUT
to ensure stability.
Battery On.
This CMOS output goes HIGH when the V
OUT
switches to V
BATT
and goes LOW when
V
OUT
switches to V
CC
. It is used to drive an external PNP pass transistor when V
CC
= V
OUT
and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to the V
OUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
7
8
V
SS
SDA
9
10
11
SCL
WP
V
BATT
12
V
OUT
13
BATT-ON
14
V
CC
Supply Voltage
4
May 25, 2006
X40420, X40421
PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40420, X40421 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V
CC
exceeds the device V
TRIP1
threshold value
for t
PURST
(selectable) the circuit releases the RESET
(X40421) and RESET (X40420) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40420, X40421
System
Reset
RESET
MR
Manual
Reset
X40421
Unreg.
Supply
5V
Reg
3V
Reg
V
CC
RESET
V2MON
V2FAIL
Notice:
No external components required to monitor two voltages.
System
Reset
Low Voltage V2 Monitoring
The X40420, X40421 also monitors a second voltage
level and asserts V2FAIL if the voltage falls below a pre-
set minimum V
TRIP2
. The V2FAIL signal is either ORed
with RESET to prevent the microprocessor from operat-
ing in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impending
power failure. The V2FAIL signal remains active until the
V
CC
drops below 1V (V
CC
falling). It also remains active
until V2MON returns and exceeds V
TRIP2
.
V2MON voltage monitor is powered by V
OUT.
If V
CC
and V
BATT
go away, V2MON cannot be monitored.
Figure 2. Two Uses of Multiple Voltage Monitoring
V
OUT
X40420
Unreg.
Supply
R
R
5V
Reg
V
CC
RESET
V2MON
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
V
OUT
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
t
PURST
or till the push-button is released and for t
PURST
thereafter. A weak pull up resistor is connected to the
MR pin.
Low Voltage V1 Monitoring
During operation, the X40420, X40421 monitors the
V
CC
level and asserts RESET if supply voltage falls
below a preset minimum V
TRIP1
. The RESET signal
prevents the microprocessor from operating in a
power fail or brownout condition. The V1FAIL signal
remains active until the voltage drops below 1V. It also
remains active until V
CC
returns and exceeds V
TRIP1
for
t
PURST
.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal to go active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40420, X40421 control reg-
ister.
5
May 25, 2006
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