Features
•
Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 50 ns
Internal Program Control and Timer
8K Bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-by-Byte Programming - 10 µs/Byte
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 30 mA Active Current
– 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
512K (64K x 8)
5-volt Only
Flash Memory
AT49F512
Description
The AT49F512 is a 5-volt-only in-system programmable and erasable Flash Memory.
Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 50
ns with a power dissipation of just 165 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F512 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the
entire 512K of memory and then programming on a byte by byte basis. The typical
byte programming time is a fast 10 µs. The end of a program cycle can be optionally
(continued)
Pin Configurations
Pin Name
A0 - A15
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
DIP Top View
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Data Inputs/Outputs
No Connect
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
512K (64K x 8)
5-volt Only
CMOS Flash
Memory
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
PLCC Top View
A12
A15
NC
NC
VCC
WE
NC
14
15
16
17
18
19
20
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
Rev. 1027D–04/99
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
1
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
FFFFH
2000H
1FFFH
0000H
Device Operation
READ:
The AT49F512 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE:
Before a byte can be reprogrammed, the 64K
bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The chip erase code
consists of 6-byte load commands to specific address loca-
tions with a specific data pattern (please refer to the Chip
Erase Cycle Waveforms).
After the chip erase has been initiated, the device will inter-
nally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is t
EC
. If the boot block lockout feature has been
enabled, the data in the boot sector will not be erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
2
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
AT49F512
AT49F512
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49F512 features DATA polling to
indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT:
In addition to DATA polling the AT49F512
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT49F512 in
the following ways: (a) V
CC
sense: if V
CC
is below 3.8V (typ-
ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
Addr
Read
Chip Erase
Byte Program
Boot Block
Lockout
(1)
Product ID
Entry
Product ID
Exit
(2)
Product ID
Exit
(2)
Notes:
1
6
4
6
3
3
1
Addr
5555
5555
5555
5555
5555
XXXX
Data
D
OUT
AA
AA
AA
AA
AA
F0
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
D
IN
AA
2AAA
55
5555
40
2AAA
55
5555
10
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3
DC and AC Operating Range
AT49F512-50
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT49F512-70
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT49F512-90
0°C - 70°C
-40°C - 85°C
5V
±
10%
Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A15 = V
IL
, A9 = V
H
, A0 = V
IL(3)
A1 - A15 = V
IL
, A9 = V
H
, A0 = V
IH(3)
A0 = V
IL
, A1 - A15 = V
IL
A0 = V
IH
, A1 - A15 = V
IL
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H
5. See details under Software Product Identification Entry/Exit.
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
Software
(5)
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC(1)
V
IL
V
IH
V
OL
V
OH1
V
OH2
Note:
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
1. In the erase mode, I
CC
is 90 mA.
I
OL
= 2.1 mA
I
OH
= -400 µA
I
OH
= -100 µA; V
CC
= 4.5V
2.4
4.2
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
Com.
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
Com.
f = 5 MHz; I
OUT
= 0 mA
Ind.
Ind.
Min
Max
10
10
100
300
3
30
40
0.8
Units
µA
µA
µA
µA
mA
mA
mA
V
V
V
V
V
4
AT49F512
AT49F512
AC Read Characteristics
AT49F512-50
Symbol
t
ACC
t
CE(1)
t
OE(2)
t
DF(3)(4)
t
OH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or
Address, whichever occurred first
0
0
Min
Max
50
50
30
25
0
0
AT49F512-70
Min
Max
70
70
35
25
0
0
0
AT49F512-90
Min
Max
90
90
40
25
Units
ns
ns
ns
ns
ns
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1.
2.
3.
4.
CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
OE may be delayed up to t
CE
- t
OE
, after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
t
R
, t
F
< 5 ns
Pin Capacitance
f = 1 MHz, T= 25°C
(1)
Symbol
C
IN
C
OUT
Note:
Typ
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. This parameter is characterized and is not 100% tested.
5
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