Features
•
Fast Read Access Time - 70 ns
•
Dual Voltage Range Operation
•
•
•
– Low Voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V
±
10% Supply Range
Compatible with JEDEC Standard AT27C512R
Low Power CMOS Operation
– 20 µA max. (less than 1 µA typical) Standby for V
CC
= 3.6V
– 29 mW max. Active at 5 MHz for V
CC
= 3.6V
JEDEC Standard Packages
– 32-Lead PLCC
– 28-Lead 330-mil SOIC
– 28-Lead TSOP
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid™ Programming Algorithm - 100 µs/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
•
•
•
•
•
512K (64K x 8)
Low Voltage
OTP EPROM
AT27LV512A
Description
The AT27LV512A is a high performance, low power, low voltage 524,288-bit one-time
programmable read only memory (OTP EPROM) organized as 64K by 8 bits. It
requires only one supply in the range of 3.0V to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.
(continued)
Pin Configurations
Pin Name
A0 - A15
O0 - O7
CE
OE/VPP
NC
Function
Addresses
Outputs
Chip Enable
Output Enable/
Program Supply
No Connect
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
SOIC Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
O7
O6
O5
O4
O3
PLCC Top View
A7
A12
A15
NC
VCC
A14
A13
TSOP Top View
Type 1
A8
A9
A11
NC
OE/VPP
A10
CE
O7
O6
OE/VPP
A11
A9
A8
A13
A14
VCC
A15
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
Note: PLCC Package Pins 1 and 17
are DON’T CONNECT.
O1
O2
GND
NC
O3
O4
O5
14
15
16
17
18
19
20
A6
A5
A4
A3
A2
A1
A0
NC
O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
Rev. 0607B–10/98
1
Atmel’s innovative design techniques provide fast speeds
that rival 5V parts while keeping the low power consump-
tion of a 3.3V supply. At V
CC
= 3.0V, any byte can be
accessed in less than 70 ns. With a typical power dissipa-
tion of only 18 mW at 5 MHz and V
C C
= 3.3V, the
AT27LV512A consumes less than one fifth the power of a
standard 5V EPROM.
Standby mode supply current is typically less than 1
µA
at
3.3V.
The AT27LV512A is available in industry standard JEDEC-
approved one-time programmable (OTP) plastic PLCC,
SOIC, and TSOP packages. All devices feature two-line
control (CE, OE) to give designers the flexibility to prevent
bus contention.
The AT27LV512A operating with V
CC
at 3.0V produces TTL
level outputs that are compatible with standard TTL logic
devices operating at V
CC
= 5.0V. The device is also capa-
ble of standard 5-volt operation making it ideally suited for
dual supply range systems or card products that are plug-
gable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV512A has additional features to ensure
high quality and efficient production use. The Rapid™ Pro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 100
µs/byte.
The Integrated
Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry
standard programming equipment to select the proper pro-
gramming algorithms and voltages. The AT27LV512A pro-
grams exactly the same way as a standard 5V AT27C512R
and uses the same programming equipment.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1
µF
high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the V
CC
and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
µF
bulk electrolytic capacitor should
be utilized, again connected between the V
CC
and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
Block Diagram
2
AT27LV512A
AT27LV512A
Absolute Maximum Ratings*
Temperature Under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Note:
1.
Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is
V
CC
+ 0.75V dc which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0 volts for pulses of less than 20 ns.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Modes
Mode \ Pin
Read
(2)
Output Disable
(2)
Standby
(2)
Rapid Program
(3)
PGM Inhibit
(3)
Product Identification
(3)(5)
Notes:
1. X can be V
IL
or V
IH
.
2. Read, output disable, and standby modes require, 3.0V
≤
V
CC
≤
3.6V, or 4.5V
≤
V
CC
≤
5.5V.
3. Refer to Programming Characteristics. Programming modes require V
CC
= 6.5V.
4. V
H
= 12.0
±
0.5V.
5. Two identifier bytes may be selected. All Ai inputs are held low (V
IL
), except A9 which is set to V
H
and A0 which is toggled low
(V
IL
) to select the Manufacturer’s Identification byte and high (V
IH
) to select the Device Code byte.
CE
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
OE/V
PP
V
IL
V
IH
X
V
PP
V
PP
V
IL
Ai
Ai
X
(1)
X
Ai
X
A9 = V
H(4)
A0 = V
IH
or V
IL
A1 - A15 = V
IL
V
CC
V
CC(2)
V
CC(2)
V
CC(2)
V
CC(3)
V
CC(3)
V
CC(3)
Outputs
D
OUT
High Z
High Z
D
IN
High Z
Identification Code
3
DC and AC Operating Conditions for Read Operation
AT27LV512A
-70
Operating Temperature
(Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
5V
±
10%
-90
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
5V
±
10%
-12
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
5V
±
10%
-15
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
5V
±
10%
DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
V
CC
= 3.0V to 3.6V
I
LI
I
LO
I
PP1(2)
I
SB
I
CC
V
IL
V
IH
V
OL
V
OH
Input Load Current
Output Leakage Current
V
PP(1)
Read/Standby Current
V
CC(1)
Standby Current
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.0 mA
I
OH
= -2.0 mA
2.4
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
V
PP
= V
CC
I
SB1
(CMOS), CE = V
CC
±
0.3V
I
SB2
(TTL), CE = 2.0 to V
CC
+ 0.5V
f = 5 MHz, I
OUT
= 0 mA, CE = V
IL
-0.6
2.0
±1
±5
10
20
100
8
0.8
V
CC
+ 0.5
0.4
µA
µA
µA
µA
µA
mA
V
V
V
V
V
CC
= 4.5V to 5.5V
I
LI
I
LO
I
PP1(2)
I
SB
I
CC
V
IL
V
IH
V
OL
V
OH
Notes:
Input Load Current
Output Leakage Current
V
PP(1)
Read/Standby Current
V
CC(1)
Standby Current
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1 mA
I
OH
= -400
µA
2.4
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
V
PP
= V
CC
I
SB1
(CMOS), CE = V
CC
±
0.3V
I
SB2
(TTL), CE = 2.0 to V
CC
+ 0.5V
f = 5 MHz, I
OUT
= 0 mA, CE = V
IL
-0.6
2.0
±1
±5
10
100
1
20
0.8
V
CC
+ 0.5
0.4
µA
µA
µA
µA
mA
mA
V
V
V
V
1. V
CC
must be applied simultaneously with or before OE/V
PP
, and removed simultaneously with or after OE/V
PP
.
2. OE/V
PP
may be connected directly to V
CC
, except during programming. The supply current would then be the sum of I
CC
and
I
PP
.
4
AT27LV512A
AT27LV512A
AC Characteristics for Read Operation
V
CC
= 3.0V to 3.6V and 4.5V to 5.5V
AT27LV512A
-70
Symbol
t
ACC(3)
t
CE(2)
t
OE(2)(3)
t
DF
(4)(5)
-90
Max
70
70
40
35
Min
Max
90
90
50
40
Min
-12
Max
120
120
50
40
Min
-15
Max
150
150
60
50
Units
ns
ns
ns
ns
Parameter
Address to Output Delay
CE to Output Delay
OE/V
PP
to Output Delay
OE/V
PP
or CE High to
Output Float, whichever
occurred first
Output Hold from Address,
CE or OE/V
PP
, whichever
occurred first
Condition
CE = OE/V
PP
= V
IL
OE/V
PP
= V
IL
CE = V
IL
Min
t
OH
0
0
0
0
ns
AC Waveforms for Read Operation
(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE/V
PP
may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
.
3. OE/V
PP
may be delayed up to t
ACC
- t
OE
after the address is valid without impact on t
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
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